Unverified Commit 0173c32a authored by Boris Brezillon's avatar Boris Brezillon Committed by Tudor Ambarus
Browse files

mtd: spi-nor: Move Spansion bits out of core.c 



Create a SPI NOR manufacturer driver for Spansion chips, and move the
Spansion definitions outside of core.c.

Signed-off-by: default avatarBoris Brezillon <bbrezillon@kernel.org>
Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
parent 15f5c7e5

drivers/mtd/spi-nor/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -11,4 +11,5 @@ spi-nor-objs += intel.o 
spi-nor-objs			+= issi.o

spi-nor-objs			+= macronix.o

spi-nor-objs			+= micron-st.o

spi-nor-objs			+= spansion.o

obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o

drivers/mtd/spi-nor/core.c

+1 −58
Original line number Diff line number Diff line
@@ -1995,44 +1995,6 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor) 
 * old entries may be missing 4K flag.

 */

static const struct flash_info spi_nor_ids[] = {

	/* Spansion/Cypress -- single (large) sector size only, at least

	 * for the chips listed here (without boot sectors).

	 */

	{ "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,

			SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },

	{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,

			SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },

	{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },

	{ "s25fl256s1", INFO(0x010219, 0x4d01,  64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },

	{ "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256,

			SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			SPI_NOR_HAS_LOCK | USE_CLSR) },

	{ "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },

	{ "s70fl01gs",  INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },

	{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64, 0) },

	{ "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256, 0) },

	{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024,  64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },

	{ "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },

	{ "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8, 0) },

	{ "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16, 0) },

	{ "s25sl016a",  INFO(0x010214,      0,  64 * 1024,  32, 0) },

	{ "s25sl032a",  INFO(0x010215,      0,  64 * 1024,  64, 0) },

	{ "s25sl064a",  INFO(0x010216,      0,  64 * 1024, 128, 0) },

	{ "s25fl004k",  INFO(0xef4013,      0,  64 * 1024,   8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25fl008k",  INFO(0xef4014,      0,  64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25fl016k",  INFO(0xef4015,      0,  64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25fl064k",  INFO(0xef4017,      0,  64 * 1024, 128, SECT_4K) },

	{ "s25fl116k",  INFO(0x014015,      0,  64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25fl132k",  INFO(0x014016,      0,  64 * 1024,  64, SECT_4K) },

	{ "s25fl164k",  INFO(0x014017,      0,  64 * 1024, 128, SECT_4K) },

	{ "s25fl204k",  INFO(0x014013,      0,  64 * 1024,   8, SECT_4K | SPI_NOR_DUAL_READ) },

	{ "s25fl208k",  INFO(0x014014,      0,  64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ) },

	{ "s25fl064l",  INFO(0x016017,      0,  64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },

	{ "s25fl128l",  INFO(0x016018,      0,  64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },

	{ "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },



	/* SST -- large erase sizes are "overlays", "sectors" are 4K */

	{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024,  8, SECT_4K | SST_WRITE) },

	{ "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
@@ -2151,6 +2113,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = { 
	&spi_nor_macronix,

	&spi_nor_micron,

	&spi_nor_st,

	&spi_nor_spansion,

};



static const struct flash_info *
@@ -3084,17 +3047,6 @@ static void spi_nor_info_init_params(struct spi_nor *nor) 
	spi_nor_init_uniform_erase_map(map, erase_mask, params->size);

}



static void spansion_post_sfdp_fixups(struct spi_nor *nor)

{

	if (nor->params.size <= SZ_16M)

		return;



	nor->flags |= SNOR_F_4B_OPCODES;

	/* No small sector erase for 4-byte command set */

	nor->erase_opcode = SPINOR_OP_SE;

	nor->mtd.erasesize = nor->info->sector_size;

}



static void s3an_post_sfdp_fixups(struct spi_nor *nor)

{

	nor->params.setup = s3an_nor_setup;
@@ -3112,15 +3064,6 @@ static void s3an_post_sfdp_fixups(struct spi_nor *nor) 
 */

static void spi_nor_post_sfdp_fixups(struct spi_nor *nor)

{

	switch (JEDEC_MFR(nor->info)) {

	case SNOR_MFR_SPANSION:

		spansion_post_sfdp_fixups(nor);

		break;



	default:

		break;

	}



	if (nor->info->flags & SPI_S3AN)

		s3an_post_sfdp_fixups(nor);

drivers/mtd/spi-nor/core.h

+1 −0
Original line number Diff line number Diff line
@@ -178,6 +178,7 @@ extern const struct spi_nor_manufacturer spi_nor_issi; 
extern const struct spi_nor_manufacturer spi_nor_macronix;

extern const struct spi_nor_manufacturer spi_nor_micron;

extern const struct spi_nor_manufacturer spi_nor_st;

extern const struct spi_nor_manufacturer spi_nor_spansion;



int spi_nor_write_enable(struct spi_nor *nor);

int spi_nor_write_disable(struct spi_nor *nor);

drivers/mtd/spi-nor/spansion.c

0 → 100644
+95 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2005, Intec Automation Inc.

 * Copyright (C) 2014, Freescale Semiconductor, Inc.

 */



#include <linux/mtd/spi-nor.h>



#include "core.h"



static const struct flash_info spansion_parts[] = {

	/* Spansion/Cypress -- single (large) sector size only, at least

	 * for the chips listed here (without boot sectors).

	 */

	{ "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64,

			     SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128,

			     SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,

			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			      USE_CLSR) },

	{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,

			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			      USE_CLSR) },

	{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },

	{ "s25fl256s1", INFO(0x010219, 0x4d01,  64 * 1024, 512,

			     SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			     USE_CLSR) },

	{ "s25fl512s",  INFO6(0x010220, 0x4d0080, 256 * 1024, 256,

			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			      SPI_NOR_HAS_LOCK | USE_CLSR) },

	{ "s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256,

			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			      USE_CLSR) },

	{ "s70fl01gs",  INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },

	{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64, 0) },

	{ "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256, 0) },

	{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024,  64,

			     SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			     USE_CLSR) },

	{ "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256,

			     SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			     USE_CLSR) },

	{ "s25sl004a",  INFO(0x010212,      0,  64 * 1024,   8, 0) },

	{ "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16, 0) },

	{ "s25sl016a",  INFO(0x010214,      0,  64 * 1024,  32, 0) },

	{ "s25sl032a",  INFO(0x010215,      0,  64 * 1024,  64, 0) },

	{ "s25sl064a",  INFO(0x010216,      0,  64 * 1024, 128, 0) },

	{ "s25fl004k",  INFO(0xef4013,      0,  64 * 1024,   8,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25fl008k",  INFO(0xef4014,      0,  64 * 1024,  16,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25fl016k",  INFO(0xef4015,      0,  64 * 1024,  32,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25fl064k",  INFO(0xef4017,      0,  64 * 1024, 128, SECT_4K) },

	{ "s25fl116k",  INFO(0x014015,      0,  64 * 1024,  32,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

	{ "s25fl132k",  INFO(0x014016,      0,  64 * 1024,  64, SECT_4K) },

	{ "s25fl164k",  INFO(0x014017,      0,  64 * 1024, 128, SECT_4K) },

	{ "s25fl204k",  INFO(0x014013,      0,  64 * 1024,   8,

			     SECT_4K | SPI_NOR_DUAL_READ) },

	{ "s25fl208k",  INFO(0x014014,      0,  64 * 1024,  16,

			     SECT_4K | SPI_NOR_DUAL_READ) },

	{ "s25fl064l",  INFO(0x016017,      0,  64 * 1024, 128,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			     SPI_NOR_4B_OPCODES) },

	{ "s25fl128l",  INFO(0x016018,      0,  64 * 1024, 256,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			     SPI_NOR_4B_OPCODES) },

	{ "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512,

			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

			     SPI_NOR_4B_OPCODES) },

};



static void spansion_post_sfdp_fixups(struct spi_nor *nor)

{

	if (nor->params.size <= SZ_16M)

		return;



	nor->flags |= SNOR_F_4B_OPCODES;

	/* No small sector erase for 4-byte command set */

	nor->erase_opcode = SPINOR_OP_SE;

	nor->mtd.erasesize = nor->info->sector_size;

}



static const struct spi_nor_fixups spansion_fixups = {

	.post_sfdp = spansion_post_sfdp_fixups,

};



const struct spi_nor_manufacturer spi_nor_spansion = {

	.name = "spansion",

	.parts = spansion_parts,

	.nparts = ARRAY_SIZE(spansion_parts),

	.fixups = &spansion_fixups,

};

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