Commit 0160e00a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC driver updates from Olof Johansson:
 "Driver updates for ARM SoCs:

  Reset subsystem, merged through arm-soc by tradition:
   - Make bool drivers explicitly non-modular
   - New support for i.MX7 and Arria10 reset controllers

  PATA driver for Palmchip BK371 (acked by Tejun)

  Power domain drivers for i.MX (GPC, GPCv2)
   - Moved out of mach-imx for GPC
   - Bunch of tweaks, fixes, etc

  PMC support for Tegra186

  SoC detection support for Renesas RZ/G1H and RZ/G1N

  Move Tegra flow controller driver from mach directory to drivers/soc
   - (Power management / CPU power driver)

  Misc smaller tweaks for other platforms"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
  soc: pm-domain: Fix the mangled urls
  soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0
  soc: renesas: rcar-sysc: Add support for fixing up power area tables
  soc: renesas: Register SoC device early
  soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
  dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
  soc: imx: gpc: add defines for domain index
  soc: imx: Add GPCv2 power gating driver
  dt-bindings: Add GPCv2 power gating driver
  ARM/clk: move the ICST library to drivers/clk
  ARM: plat-versatile: remove stale clock header
  ARM: keystone: Drop PM domain support for k2g
  soc: ti: Add ti_sci_pm_domains driver
  dt-bindings: Add TI SCI PM Domains
  PM / Domains: Do not check if simple providers have phandle cells
  PM / Domains: Add generic data pointer to genpd data struct
  soc/tegra: Add initial flowctrl support for Tegra132/210
  soc/tegra: flowctrl: Add basic platform driver
  soc/tegra: Move Tegra flowctrl driver
  ARM: tegra: Remove unnecessary inclusion of flowctrl header
  ...
parents c81ee18e b6942b68

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt

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NVIDIA Tegra Power Management Controller (PMC)



Required properties:

- compatible: Should contain one of the following:

  - "nvidia,tegra186-pmc": for Tegra186

- reg: Must contain an (offset, length) pair of the register set for each

  entry in reg-names.

- reg-names: Must include the following entries:

  - "pmc"

  - "wake"

  - "aotag"

  - "scratch"



Optional properties:

- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.



Example:



SoC DTSI:



	pmc@c3600000 {

		compatible = "nvidia,tegra186-pmc";

		reg = <0 0x0c360000 0 0x10000>,

		      <0 0x0c370000 0 0x10000>,

		      <0 0x0c380000 0 0x10000>,

		      <0 0x0c390000 0 0x10000>;

		reg-names = "pmc", "wake", "aotag", "scratch";

	};



Board DTS:



	pmc@c360000 {

		nvidia,invert-interrupt;

	};

Documentation/devicetree/bindings/power/fsl,imx-gpc.txt

+57 −28
Original line number Diff line number Diff line 
Freescale i.MX General Power Controller

=======================================



The i.MX6Q General Power Control (GPC) block contains DVFS load tracking

counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power

domains.

The i.MX6 General Power Control (GPC) block contains DVFS load tracking

counters and Power Gating Control (PGC).



Required properties:

- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"

- compatible: Should be one of the following:

  - fsl,imx6q-gpc

  - fsl,imx6qp-gpc

  - fsl,imx6sl-gpc

- reg: should be register base and length as documented in the

  datasheet

- interrupts: Should contain GPC interrupt request 1

- pu-supply: Link to the LDO regulator powering the PU power domain

- clocks: Clock phandles to devices in the PU power domain that need

	  to be enabled during domain power-up for reset propagation.

- #power-domain-cells: Should be 1, see below:

- interrupts: Should contain one interrupt specifier for the GPC interrupt

- clocks: Must contain an entry for each entry in clock-names.

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - ipg



The gpc node is a power-controller as documented by the generic power domain

bindings in Documentation/devicetree/bindings/power/power_domain.txt.

The power domains are generic power domain providers as documented in

Documentation/devicetree/bindings/power/power_domain.txt. They are described as

subnodes of the power gating controller 'pgc' node of the GPC and should

contain the following:



Required properties:

- reg: Must contain the DOMAIN_INDEX of this power domain

  The following DOMAIN_INDEX values are valid for i.MX6Q:

  ARM_DOMAIN     0

  PU_DOMAIN      1

  The following additional DOMAIN_INDEX value is valid for i.MX6SL:

  DISPLAY_DOMAIN 2



- #power-domain-cells: Should be 0



Optional properties:

- clocks: a number of phandles to clocks that need to be enabled during domain

  power-up sequencing to ensure reset propagation into devices located inside

  this power domain

- power-supply: a phandle to the regulator powering this domain



Example:
@@ -25,14 +45,30 @@ Example: 
		reg = <0x020dc000 0x4000>;

		interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,

			     <0 90 IRQ_TYPE_LEVEL_HIGH>;

		pu-supply = <&reg_pu>;

		clocks = <&clks IMX6QDL_CLK_IPG>;

		clock-names = "ipg";



		pgc {

			#address-cells = <1>;

			#size-cells = <0>;



			power-domain@0 {

				reg = <0>;

				#power-domain-cells = <0>;

			};



			pd_pu: power-domain@1 {

				reg = <1>;

				#power-domain-cells = <0>;

				power-supply = <&reg_pu>;

				clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,

				         <&clks IMX6QDL_CLK_GPU3D_SHADER>,

				         <&clks IMX6QDL_CLK_GPU2D_CORE>,

				         <&clks IMX6QDL_CLK_GPU2D_AXI>,

				         <&clks IMX6QDL_CLK_OPENVG_AXI>,

				         <&clks IMX6QDL_CLK_VPU_AXI>;

		#power-domain-cells = <1>;

			};

		};

	};
@@ -40,20 +76,13 @@ Specifying power domain for IP modules 
======================================



IP cores belonging to a power domain should contain a 'power-domains' property

that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying

the power domain the device belongs to.

that is a phandle pointing to the power domain the device belongs to.



Example of a device that is part of the PU power domain:



	vpu: vpu@02040000 {

		reg = <0x02040000 0x3c000>;

		/* ... */

		power-domains = <&gpc 1>;

		power-domains = <&pd_pu>;

		/* ... */

	};
 


The following DOMAIN_INDEX values are valid for i.MX6Q:

ARM_DOMAIN     0

PU_DOMAIN      1

The following additional DOMAIN_INDEX value is valid for i.MX6SL:

DISPLAY_DOMAIN 2

Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt

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Freescale i.MX General Power Controller v2

==========================================



The i.MX7S/D General Power Control (GPC) block contains Power Gating

Control (PGC) for various power domains.



Required properties:



- compatible: Should be "fsl,imx7d-gpc"



- reg: should be register base and length as documented in the

  datasheet



- interrupts: Should contain GPC interrupt request 1



Power domains contained within GPC node are generic power domain

providers, documented in

Documentation/devicetree/bindings/power/power_domain.txt, which are

described as subnodes of the power gating controller 'pgc' node,

which, in turn, is expected to contain the following:



Required properties:



- reg: Power domain index. Valid values are defined in

  include/dt-bindings/power/imx7-power.h



- #power-domain-cells: Should be 0



Optional properties:



- power-supply: Power supply used to power the domain



Example:



	gpc: gpc@303a0000 {

		compatible = "fsl,imx7d-gpc";

		reg = <0x303a0000 0x1000>;

		interrupt-controller;

		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;

		#interrupt-cells = <3>;

		interrupt-parent = <&intc>;



		pgc {

			#address-cells = <1>;

			#size-cells = <0>;



			pgc_pcie_phy: power-domain@3 {

				#power-domain-cells = <0>;



				reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;

				power-supply = <&reg_1p0d>;

			};

		};

	};





Specifying power domain for IP modules

======================================



IP cores belonging to a power domain should contain a 'power-domains'

property that is a phandle for PGC node representing the domain.



Example of a device that is part of the PCIE_PHY power domain:



	pcie: pcie@33800000 {

	      reg = <0x33800000 0x4000>,

	            <0x4ff00000 0x80000>;

		/* ... */

		power-domains = <&pgc_pcie_phy>;

		/* ... */

	};

Documentation/devicetree/bindings/reset/fsl,imx7-src.txt

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Freescale i.MX7 System Reset Controller

======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: Should be "fsl,imx7-src", "syscon"

- reg: should be register base and length as documented in the

  datasheet

- interrupts: Should contain SRC interrupt

- #reset-cells: 1, see below



example:



src: reset-controller@30390000 {

     compatible = "fsl,imx7d-src", "syscon";

     reg = <0x30390000 0x2000>;

     interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

     #reset-cells = <1>;

};





Specifying reset lines connected to IP modules

==============================================



The system reset controller can be used to reset various set of

peripherals. Device nodes that need access to reset lines should

specify them as a reset phandle in their corresponding node as

specified in reset.txt.



Example:



	pcie: pcie@33800000 {



		...



		resets = <&src IMX7_RESET_PCIEPHY>,

			 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;

		reset-names = "pciephy", "apps";



		...

        };





For list of all valid reset indicies see

<dt-bindings/reset/imx7-reset.h>

Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt

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Texas Instruments TI-SCI Generic Power Domain

---------------------------------------------



Some TI SoCs contain a system controller (like the PMMC, etc...) that is

responsible for controlling the state of the IPs that are present.

Communication between the host processor running an OS and the system

controller happens through a protocol known as TI-SCI [1].



[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt



PM Domain Node

==============

The PM domain node represents the global PM domain managed by the PMMC, which

in this case is the implementation as documented by the generic PM domain

bindings in Documentation/devicetree/bindings/power/power_domain.txt.  Because

this relies on the TI SCI protocol to communicate with the PMMC it must be a

child of the pmmc node.



Required Properties:

--------------------

- compatible: should be "ti,sci-pm-domain"

- #power-domain-cells: Must be 1 so that an id can be provided in each

		       device node.



Example (K2G):

-------------

	pmmc: pmmc {

		compatible = "ti,k2g-sci";

		...



		k2g_pds: power-controller {

			compatible = "ti,sci-pm-domain";

			#power-domain-cells = <1>;

		};

	};



PM Domain Consumers

===================

Hardware blocks belonging to a PM domain should contain a "power-domains"

property that is a phandle pointing to the corresponding PM domain node

along with an index representing the device id to be passed to the PMMC

for device control.



Required Properties:

--------------------

- power-domains: phandle pointing to the corresponding PM domain node

		 and an ID representing the device.



See dt-bindings/genpd/k2g.h for the list of valid identifiers for k2g.



Example (K2G):

--------------------

	uart0: serial@02530c00 {

		compatible = "ns16550a";

		...

		power-domains = <&k2g_pds K2G_DEV_UART0>;

	};

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