Commit 013b1857 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v5.2-tag1' of... 

Merge tag 'clk-renesas-for-v5.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull renesas clk driver updates from Geert Uytterhoeven:

  - Add missing PCI USB clock on RZ/N1
  - Add Z2 (Cortex-A53) clocks on R-Car E3 and RZ/G2E, incl. a new
    helper in <linux/math64.h>

* tag 'clk-renesas-for-v5.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value
  clk: renesas: r8a77980: Fix RPC-IF module clock's parent
  clk: renesas: rcar-gen3: Rename DRIF clocks
  clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
  clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
  clk: renesas: rcar-gen3: Correct parent clock of HS-USB
  clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
  clk: renesas: r8a774c0: Add Z2 clock
  clk: renesas: r8a77990: Add Z2 clock
  clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents
  math64: New DIV64_U64_ROUND_CLOSEST helper
  clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2
  clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
  clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
  clk: renesas: r9a06g032: Add missing PCI USB clock
  clk: renesas: r7s9210: Always use readl()
  clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()
parents 9e98c678 b953eaae

drivers/clk/renesas/r7s9210-cpg-mssr.c

+2 −1
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 


#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/io.h>

#include <dt-bindings/clock/r7s9210-cpg-mssr.h>

#include "renesas-cpg-mssr.h"
@@ -119,7 +120,7 @@ static void __init r7s9210_update_clk_table(struct clk *extal_clk, 
	if (clk_get_rate(extal_clk) > 12000000)

		cpg_mode = 1;



	frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;

	frqcr = readl(base + CPG_FRQCR) & 0xFFF;

	if (frqcr == 0x012)

		index = 0;

	else if (frqcr == 0x112)

drivers/clk/renesas/r8a774a1-cpg-mssr.c

+9 −9
Original line number Diff line number Diff line
@@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { 
	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),



	/* Core Clock Outputs */

	DEF_BASE("z",           R8A774A1_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),

	DEF_BASE("z2",          R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),

	DEF_GEN3_Z("z",		R8A774A1_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),

	DEF_GEN3_Z("z2",	R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),

	DEF_FIXED("ztr",        R8A774A1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A774A1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -123,8 +123,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { 
	DEF_MOD("msiof2",		 209,	R8A774A1_CLK_MSO),

	DEF_MOD("msiof1",		 210,	R8A774A1_CLK_MSO),

	DEF_MOD("msiof0",		 211,	R8A774A1_CLK_MSO),

	DEF_MOD("sys-dmac2",		 217,	R8A774A1_CLK_S0D3),

	DEF_MOD("sys-dmac1",		 218,	R8A774A1_CLK_S0D3),

	DEF_MOD("sys-dmac2",		 217,	R8A774A1_CLK_S3D1),

	DEF_MOD("sys-dmac1",		 218,	R8A774A1_CLK_S3D1),

	DEF_MOD("sys-dmac0",		 219,	R8A774A1_CLK_S0D3),

	DEF_MOD("cmt3",			 300,	R8A774A1_CLK_R),

	DEF_MOD("cmt2",			 301,	R8A774A1_CLK_R),
@@ -143,8 +143,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { 
	DEF_MOD("rwdt",			 402,	R8A774A1_CLK_R),

	DEF_MOD("intc-ex",		 407,	R8A774A1_CLK_CP),

	DEF_MOD("intc-ap",		 408,	R8A774A1_CLK_S0D3),

	DEF_MOD("audmac1",		 501,	R8A774A1_CLK_S0D3),

	DEF_MOD("audmac0",		 502,	R8A774A1_CLK_S0D3),

	DEF_MOD("audmac1",		 501,	R8A774A1_CLK_S1D2),

	DEF_MOD("audmac0",		 502,	R8A774A1_CLK_S1D2),

	DEF_MOD("hscif4",		 516,	R8A774A1_CLK_S3D1),

	DEF_MOD("hscif3",		 517,	R8A774A1_CLK_S3D1),

	DEF_MOD("hscif2",		 518,	R8A774A1_CLK_S3D1),
@@ -165,9 +165,9 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { 
	DEF_MOD("vspd0",		 623,	R8A774A1_CLK_S0D2),

	DEF_MOD("vspb",			 626,	R8A774A1_CLK_S0D1),

	DEF_MOD("vspi0",		 631,	R8A774A1_CLK_S0D1),

	DEF_MOD("ehci1",		 702,	R8A774A1_CLK_S3D4),

	DEF_MOD("ehci0",		 703,	R8A774A1_CLK_S3D4),

	DEF_MOD("hsusb",		 704,	R8A774A1_CLK_S3D4),

	DEF_MOD("ehci1",		 702,	R8A774A1_CLK_S3D2),

	DEF_MOD("ehci0",		 703,	R8A774A1_CLK_S3D2),

	DEF_MOD("hsusb",		 704,	R8A774A1_CLK_S3D2),

	DEF_MOD("csi20",		 714,	R8A774A1_CLK_CSI0),

	DEF_MOD("csi40",		 716,	R8A774A1_CLK_CSI0),

	DEF_MOD("du2",			 722,	R8A774A1_CLK_S2D1),

drivers/clk/renesas/r8a774c0-cpg-mssr.c

+4 −3
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { 
	/* Core Clock Outputs */

	DEF_FIXED("za2",       R8A774C0_CLK_ZA2,   CLK_PLL0D24,    1, 1),

	DEF_FIXED("za8",       R8A774C0_CLK_ZA8,   CLK_PLL0D8,     1, 1),

	DEF_GEN3_Z("z2",       R8A774C0_CLK_Z2,    CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),

	DEF_FIXED("ztr",       R8A774C0_CLK_ZTR,   CLK_PLL1,       6, 1),

	DEF_FIXED("zt",        R8A774C0_CLK_ZT,    CLK_PLL1,       4, 1),

	DEF_FIXED("zx",        R8A774C0_CLK_ZX,    CLK_PLL1,       3, 1),
@@ -157,7 +158,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { 
	DEF_MOD("intc-ex",		 407,	R8A774C0_CLK_CP),

	DEF_MOD("intc-ap",		 408,	R8A774C0_CLK_S0D3),



	DEF_MOD("audmac0",		 502,	R8A774C0_CLK_S3D4),

	DEF_MOD("audmac0",		 502,	R8A774C0_CLK_S1D2),

	DEF_MOD("hscif4",		 516,	R8A774C0_CLK_S3D1C),

	DEF_MOD("hscif3",		 517,	R8A774C0_CLK_S3D1C),

	DEF_MOD("hscif2",		 518,	R8A774C0_CLK_S3D1C),
@@ -177,8 +178,8 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = { 
	DEF_MOD("vspb",			 626,	R8A774C0_CLK_S0D1),

	DEF_MOD("vspi0",		 631,	R8A774C0_CLK_S0D1),



	DEF_MOD("ehci0",		 703,	R8A774C0_CLK_S3D4),

	DEF_MOD("hsusb",		 704,	R8A774C0_CLK_S3D4),

	DEF_MOD("ehci0",		 703,	R8A774C0_CLK_S3D2),

	DEF_MOD("hsusb",		 704,	R8A774C0_CLK_S3D2),

	DEF_MOD("csi40",		 716,	R8A774C0_CLK_CSI0),

	DEF_MOD("du1",			 723,	R8A774C0_CLK_S1D1),

	DEF_MOD("du0",			 724,	R8A774C0_CLK_S1D1),

drivers/clk/renesas/r8a7795-cpg-mssr.c

+21 −20
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset

 *

 * Copyright (C) 2015 Glider bvba

 * Copyright (C) 2018-2019 Renesas Electronics Corp.

 *

 * Based on clk-rcar-gen3.c

 *
@@ -73,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { 
	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),



	/* Core Clock Outputs */

	DEF_BASE("z",           R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),

	DEF_BASE("z2",          R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),

	DEF_GEN3_Z("z",         R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),

	DEF_GEN3_Z("z2",        R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),

	DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -129,8 +130,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 
	DEF_MOD("msiof2",		 209,	R8A7795_CLK_MSO),

	DEF_MOD("msiof1",		 210,	R8A7795_CLK_MSO),

	DEF_MOD("msiof0",		 211,	R8A7795_CLK_MSO),

	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S0D3),

	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S0D3),

	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S3D1),

	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S3D1),

	DEF_MOD("sys-dmac0",		 219,	R8A7795_CLK_S0D3),

	DEF_MOD("sceg-pub",		 229,	R8A7795_CLK_CR),

	DEF_MOD("cmt3",			 300,	R8A7795_CLK_R),
@@ -153,16 +154,16 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 
	DEF_MOD("rwdt",			 402,	R8A7795_CLK_R),

	DEF_MOD("intc-ex",		 407,	R8A7795_CLK_CP),

	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S0D3),

	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S0D3),

	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S0D3),

	DEF_MOD("drif7",		 508,	R8A7795_CLK_S3D2),

	DEF_MOD("drif6",		 509,	R8A7795_CLK_S3D2),

	DEF_MOD("drif5",		 510,	R8A7795_CLK_S3D2),

	DEF_MOD("drif4",		 511,	R8A7795_CLK_S3D2),

	DEF_MOD("drif3",		 512,	R8A7795_CLK_S3D2),

	DEF_MOD("drif2",		 513,	R8A7795_CLK_S3D2),

	DEF_MOD("drif1",		 514,	R8A7795_CLK_S3D2),

	DEF_MOD("drif0",		 515,	R8A7795_CLK_S3D2),

	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S1D2),

	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S1D2),

	DEF_MOD("drif31",		 508,	R8A7795_CLK_S3D2),

	DEF_MOD("drif30",		 509,	R8A7795_CLK_S3D2),

	DEF_MOD("drif21",		 510,	R8A7795_CLK_S3D2),

	DEF_MOD("drif20",		 511,	R8A7795_CLK_S3D2),

	DEF_MOD("drif11",		 512,	R8A7795_CLK_S3D2),

	DEF_MOD("drif10",		 513,	R8A7795_CLK_S3D2),

	DEF_MOD("drif01",		 514,	R8A7795_CLK_S3D2),

	DEF_MOD("drif00",		 515,	R8A7795_CLK_S3D2),

	DEF_MOD("hscif4",		 516,	R8A7795_CLK_S3D1),

	DEF_MOD("hscif3",		 517,	R8A7795_CLK_S3D1),

	DEF_MOD("hscif2",		 518,	R8A7795_CLK_S3D1),
@@ -194,12 +195,12 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 
	DEF_MOD("vspi2",		 629,	R8A7795_CLK_S2D1), /* ES1.x */

	DEF_MOD("vspi1",		 630,	R8A7795_CLK_S0D1),

	DEF_MOD("vspi0",		 631,	R8A7795_CLK_S0D1),

	DEF_MOD("ehci3",		 700,	R8A7795_CLK_S3D4),

	DEF_MOD("ehci2",		 701,	R8A7795_CLK_S3D4),

	DEF_MOD("ehci1",		 702,	R8A7795_CLK_S3D4),

	DEF_MOD("ehci0",		 703,	R8A7795_CLK_S3D4),

	DEF_MOD("hsusb",		 704,	R8A7795_CLK_S3D4),

	DEF_MOD("hsusb3",		 705,	R8A7795_CLK_S3D4),

	DEF_MOD("ehci3",		 700,	R8A7795_CLK_S3D2),

	DEF_MOD("ehci2",		 701,	R8A7795_CLK_S3D2),

	DEF_MOD("ehci1",		 702,	R8A7795_CLK_S3D2),

	DEF_MOD("ehci0",		 703,	R8A7795_CLK_S3D2),

	DEF_MOD("hsusb",		 704,	R8A7795_CLK_S3D2),

	DEF_MOD("hsusb3",		 705,	R8A7795_CLK_S3D2),

	DEF_MOD("csi21",		 713,	R8A7795_CLK_CSI0), /* ES1.x */

	DEF_MOD("csi20",		 714,	R8A7795_CLK_CSI0),

	DEF_MOD("csi41",		 715,	R8A7795_CLK_CSI0),

drivers/clk/renesas/r8a7796-cpg-mssr.c

+18 −17
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset

 *

 * Copyright (C) 2016 Glider bvba

 * Copyright (C) 2018 Renesas Electronics Corp.

 *

 * Based on r8a7795-cpg-mssr.c

 *
@@ -73,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 
	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),



	/* Core Clock Outputs */

	DEF_BASE("z",           R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),

	DEF_BASE("z2",          R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),

	DEF_GEN3_Z("z",         R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),

	DEF_GEN3_Z("z2",        R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),

	DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -126,8 +127,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("msiof2",		 209,	R8A7796_CLK_MSO),

	DEF_MOD("msiof1",		 210,	R8A7796_CLK_MSO),

	DEF_MOD("msiof0",		 211,	R8A7796_CLK_MSO),

	DEF_MOD("sys-dmac2",		 217,	R8A7796_CLK_S0D3),

	DEF_MOD("sys-dmac1",		 218,	R8A7796_CLK_S0D3),

	DEF_MOD("sys-dmac2",		 217,	R8A7796_CLK_S3D1),

	DEF_MOD("sys-dmac1",		 218,	R8A7796_CLK_S3D1),

	DEF_MOD("sys-dmac0",		 219,	R8A7796_CLK_S0D3),

	DEF_MOD("cmt3",			 300,	R8A7796_CLK_R),

	DEF_MOD("cmt2",			 301,	R8A7796_CLK_R),
@@ -146,16 +147,16 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("rwdt",			 402,	R8A7796_CLK_R),

	DEF_MOD("intc-ex",		 407,	R8A7796_CLK_CP),

	DEF_MOD("intc-ap",		 408,	R8A7796_CLK_S0D3),

	DEF_MOD("audmac1",		 501,	R8A7796_CLK_S0D3),

	DEF_MOD("audmac0",		 502,	R8A7796_CLK_S0D3),

	DEF_MOD("drif7",		 508,	R8A7796_CLK_S3D2),

	DEF_MOD("drif6",		 509,	R8A7796_CLK_S3D2),

	DEF_MOD("drif5",		 510,	R8A7796_CLK_S3D2),

	DEF_MOD("drif4",		 511,	R8A7796_CLK_S3D2),

	DEF_MOD("drif3",		 512,	R8A7796_CLK_S3D2),

	DEF_MOD("drif2",		 513,	R8A7796_CLK_S3D2),

	DEF_MOD("drif1",		 514,	R8A7796_CLK_S3D2),

	DEF_MOD("drif0",		 515,	R8A7796_CLK_S3D2),

	DEF_MOD("audmac1",		 501,	R8A7796_CLK_S1D2),

	DEF_MOD("audmac0",		 502,	R8A7796_CLK_S1D2),

	DEF_MOD("drif31",		 508,	R8A7796_CLK_S3D2),

	DEF_MOD("drif30",		 509,	R8A7796_CLK_S3D2),

	DEF_MOD("drif21",		 510,	R8A7796_CLK_S3D2),

	DEF_MOD("drif20",		 511,	R8A7796_CLK_S3D2),

	DEF_MOD("drif11",		 512,	R8A7796_CLK_S3D2),

	DEF_MOD("drif10",		 513,	R8A7796_CLK_S3D2),

	DEF_MOD("drif01",		 514,	R8A7796_CLK_S3D2),

	DEF_MOD("drif00",		 515,	R8A7796_CLK_S3D2),

	DEF_MOD("hscif4",		 516,	R8A7796_CLK_S3D1),

	DEF_MOD("hscif3",		 517,	R8A7796_CLK_S3D1),

	DEF_MOD("hscif2",		 518,	R8A7796_CLK_S3D1),
@@ -176,9 +177,9 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("vspd0",		 623,	R8A7796_CLK_S0D2),

	DEF_MOD("vspb",			 626,	R8A7796_CLK_S0D1),

	DEF_MOD("vspi0",		 631,	R8A7796_CLK_S0D1),

	DEF_MOD("ehci1",		 702,	R8A7796_CLK_S3D4),

	DEF_MOD("ehci0",		 703,	R8A7796_CLK_S3D4),

	DEF_MOD("hsusb",		 704,	R8A7796_CLK_S3D4),

	DEF_MOD("ehci1",		 702,	R8A7796_CLK_S3D2),

	DEF_MOD("ehci0",		 703,	R8A7796_CLK_S3D2),

	DEF_MOD("hsusb",		 704,	R8A7796_CLK_S3D2),

	DEF_MOD("csi20",		 714,	R8A7796_CLK_CSI0),

	DEF_MOD("csi40",		 716,	R8A7796_CLK_CSI0),

	DEF_MOD("du2",			 722,	R8A7796_CLK_S2D1),

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