Commit 01302f5b authored by Sara Sharon's avatar Sara Sharon Committed by Luca Coelho
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iwlwifi: Revert "iwlwifi: pcie: dynamic Tx command queue size"



This reverts commit dd05f9aa.

Shorter TX queues support was added eventually without the
need for the parameters this patch added.

Signed-off-by: default avatarSara Sharon <sara.sharon@intel.com>
Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
parent e0498146
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+0 −1
Original line number Diff line number Diff line
@@ -137,7 +137,6 @@ static const struct iwl_ht_params iwl_22000_ht_params = {
	.gen2 = true,							\
	.nvm_type = IWL_NVM_EXT,					\
	.dbgc_supported = true,						\
	.tx_cmd_queue_size = 32,					\
	.min_umac_error_event_table = 0x400000

const struct iwl_cfg iwl22000_2ac_cfg_hr = {
+0 −3
Original line number Diff line number Diff line
@@ -333,8 +333,6 @@ struct iwl_pwr_tx_backoff {
 * @gen2: 22000 and on transport operation
 * @cdb: CDB support
 * @nvm_type: see &enum iwl_nvm_type
 * @tx_cmd_queue_size: size of the cmd queue. If zero, use the same value as
 *	the regular queues
 *
 * We enable the driver to be backward compatible wrt. hardware features.
 * API differences in uCode shouldn't be handled here but through TLVs
@@ -386,7 +384,6 @@ struct iwl_cfg {
	    gen2:1,
	    cdb:1,
	    dbgc_supported:1;
	u16 tx_cmd_queue_size;
	u8 valid_tx_ant;
	u8 valid_rx_ant;
	u8 non_shared_ant;
+1 −1
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
	ctxt_info->hcmd_cfg.cmd_queue_addr =
		cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
	ctxt_info->hcmd_cfg.cmd_queue_size =
		TFD_QUEUE_CB_SIZE(trans_pcie->tx_cmd_queue_size);
		TFD_QUEUE_CB_SIZE(TFD_CMD_SLOTS);

	/* allocate ucode sections in dram and set addresses */
	ret = iwl_pcie_ctxt_info_init_fw_sec(trans, fw, ctxt_info);
+0 −3
Original line number Diff line number Diff line
@@ -383,7 +383,6 @@ struct iwl_self_init_dram {
 * @hw_init_mask: initial unmasked hw causes
 * @fh_mask: current unmasked fh causes
 * @hw_mask: current unmasked hw causes
 * @tx_cmd_queue_size: the size of the tx command queue
 */
struct iwl_trans_pcie {
	struct iwl_rxq *rxq;
@@ -465,7 +464,6 @@ struct iwl_trans_pcie {
	u32 fh_mask;
	u32 hw_mask;
	cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
	u16 tx_cmd_queue_size;
};

static inline struct iwl_trans_pcie *
@@ -537,7 +535,6 @@ void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
			    struct sk_buff_head *skbs);
void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
void iwl_pcie_set_tx_cmd_queue_size(struct iwl_trans *trans);

static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd,
					  u8 idx)
+2 −6
Original line number Diff line number Diff line
@@ -1173,8 +1173,6 @@ int iwl_pcie_gen2_tx_init(struct iwl_trans *trans)
	struct iwl_txq *cmd_queue;
	int txq_id = trans_pcie->cmd_queue, ret;

	iwl_pcie_set_tx_cmd_queue_size(trans);

	/* alloc and init the command queue */
	if (!trans_pcie->txq[txq_id]) {
		cmd_queue = kzalloc(sizeof(*cmd_queue), GFP_KERNEL);
@@ -1183,8 +1181,7 @@ int iwl_pcie_gen2_tx_init(struct iwl_trans *trans)
			return -ENOMEM;
		}
		trans_pcie->txq[txq_id] = cmd_queue;
		ret = iwl_pcie_txq_alloc(trans, cmd_queue,
					 trans_pcie->tx_cmd_queue_size, true);
		ret = iwl_pcie_txq_alloc(trans, cmd_queue, TFD_CMD_SLOTS, true);
		if (ret) {
			IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
			goto error;
@@ -1193,8 +1190,7 @@ int iwl_pcie_gen2_tx_init(struct iwl_trans *trans)
		cmd_queue = trans_pcie->txq[txq_id];
	}

	ret = iwl_pcie_txq_init(trans, cmd_queue,
				trans_pcie->tx_cmd_queue_size, true);
	ret = iwl_pcie_txq_init(trans, cmd_queue, TFD_CMD_SLOTS, true);
	if (ret) {
		IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
		goto error;
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