Commit 0113340e authored by Will Deacon's avatar Will Deacon
Browse files

arm64: cpufeature: Spell out register fields for ID_ISAR4 and ID_PFR1 



In preparation for runtime updates to the strictness of some AArch32
features, spell out the register fields for ID_ISAR4 and ID_PFR1 to make
things clearer to read. Note that this isn't functionally necessary, as
the feature arrays themselves are not modified dynamically and remain
'const'.

Tested-by: default avatarSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20200421142922.18950-3-will@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 9d3f8881

arch/arm64/include/asm/sysreg.h

+17 −0
Original line number Diff line number Diff line
@@ -752,6 +752,15 @@ 


#define ID_DFR0_PERFMON_8_1		0x4



#define ID_ISAR4_SWP_FRAC_SHIFT		28

#define ID_ISAR4_PSR_M_SHIFT		24

#define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT	20

#define ID_ISAR4_BARRIER_SHIFT		16

#define ID_ISAR4_SMC_SHIFT		12

#define ID_ISAR4_WRITEBACK_SHIFT	8

#define ID_ISAR4_WITHSHIFTS_SHIFT	4

#define ID_ISAR4_UNPRIV_SHIFT		0



#define ID_ISAR5_RDM_SHIFT		24

#define ID_ISAR5_CRC32_SHIFT		16

#define ID_ISAR5_SHA2_SHIFT		12
@@ -785,6 +794,14 @@ 
#define MVFR1_FPDNAN_SHIFT		4

#define MVFR1_FPFTZ_SHIFT		0



#define ID_PFR1_GIC_SHIFT		28

#define ID_PFR1_VIRT_FRAC_SHIFT		24

#define ID_PFR1_SEC_FRAC_SHIFT		20

#define ID_PFR1_GENTIMER_SHIFT		16

#define ID_PFR1_VIRTUALIZATION_SHIFT	12

#define ID_PFR1_MPROGMOD_SHIFT		8

#define ID_PFR1_SECURITY_SHIFT		4

#define ID_PFR1_PROGMOD_SHIFT		0



#define ID_AA64MMFR0_TGRAN4_SHIFT	28

#define ID_AA64MMFR0_TGRAN64_SHIFT	24

arch/arm64/kernel/cpufeature.c

+26 −2
Original line number Diff line number Diff line
@@ -332,6 +332,18 @@ static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 
	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_isar4[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_isar6[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
@@ -351,6 +363,18 @@ static const struct arm64_ftr_bits ftr_id_pfr0[] = { 
	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_pfr1[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_dfr0[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),

	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),	/* PerfMon */
@@ -411,7 +435,7 @@ static const struct __ftr_reg_entry { 


	/* Op1 = 0, CRn = 0, CRm = 1 */

	ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),

	ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),

	ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),

	ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),

	ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
@@ -423,7 +447,7 @@ static const struct __ftr_reg_entry { 
	ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),

	ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),

	ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),

	ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),

	ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),

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