drm/i915/dsc: rename crtc state dsc_params member to dsc (010663a6) · Commits · 戴 / test

drivers/gpu/drm/i915/display/intel_ddi.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -2234,7 +2234,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
	/*		/*
	* VDSC power is needed when DSC is enabled		* VDSC power is needed when DSC is enabled
	*/		*/
	if (crtc_state->dsc_params.compression_enable)		if (crtc_state->dsc.compression_enable)
	intel_display_power_get(dev_priv,		intel_display_power_get(dev_priv,
	intel_dsc_power_domain(crtc_state));		intel_dsc_power_domain(crtc_state));
	}		}

drivers/gpu/drm/i915/display/intel_display_types.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -986,7 +986,7 @@ struct intel_crtc_state {
	bool dsc_split;		bool dsc_split;
	u16 compressed_bpp;		u16 compressed_bpp;
	u8 slice_count;		u8 slice_count;
	} dsc_params;		} dsc;
	struct drm_dsc_config dp_dsc_cfg;		struct drm_dsc_config dp_dsc_cfg;

	/* Forward Error correction State */		/* Forward Error correction State */

drivers/gpu/drm/i915/display/intel_dp.c

+16 −16

Original line number	Original line	Diff line number	Diff line
	@@ -2080,10 +2080,10 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
	pipe_config->lane_count = limits->max_lane_count;		pipe_config->lane_count = limits->max_lane_count;

	if (intel_dp_is_edp(intel_dp)) {		if (intel_dp_is_edp(intel_dp)) {
	pipe_config->dsc_params.compressed_bpp =		pipe_config->dsc.compressed_bpp =
	min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,		min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
	pipe_config->pipe_bpp);		pipe_config->pipe_bpp);
	pipe_config->dsc_params.slice_count =		pipe_config->dsc.slice_count =
	drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,		drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
	true);		true);
	} else {		} else {
	@@ -2104,10 +2104,10 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
	DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");		DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
	return -EINVAL;		return -EINVAL;
	}		}
	pipe_config->dsc_params.compressed_bpp = min_t(u16,		pipe_config->dsc.compressed_bpp = min_t(u16,
	dsc_max_output_bpp >> 4,		dsc_max_output_bpp >> 4,
	pipe_config->pipe_bpp);		pipe_config->pipe_bpp);
	pipe_config->dsc_params.slice_count = dsc_dp_slice_count;		pipe_config->dsc.slice_count = dsc_dp_slice_count;
	}		}
	/*		/*
	* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate		* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
	@@ -2115,8 +2115,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
	* then we need to use 2 VDSC instances.		* then we need to use 2 VDSC instances.
	*/		*/
	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {		if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
	if (pipe_config->dsc_params.slice_count > 1) {		if (pipe_config->dsc.slice_count > 1) {
	pipe_config->dsc_params.dsc_split = true;		pipe_config->dsc.dsc_split = true;
	} else {		} else {
	DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");		DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
	return -EINVAL;		return -EINVAL;
	@@ -2128,16 +2128,16 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
	DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "		DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
	"Compressed BPP = %d\n",		"Compressed BPP = %d\n",
	pipe_config->pipe_bpp,		pipe_config->pipe_bpp,
	pipe_config->dsc_params.compressed_bpp);		pipe_config->dsc.compressed_bpp);
	return ret;		return ret;
	}		}

	pipe_config->dsc_params.compression_enable = true;		pipe_config->dsc.compression_enable = true;
	DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "		DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
	"Compressed Bpp = %d Slice Count = %d\n",		"Compressed Bpp = %d Slice Count = %d\n",
	pipe_config->pipe_bpp,		pipe_config->pipe_bpp,
	pipe_config->dsc_params.compressed_bpp,		pipe_config->dsc.compressed_bpp,
	pipe_config->dsc_params.slice_count);		pipe_config->dsc.slice_count);

	return 0;		return 0;
	}		}
	@@ -2211,15 +2211,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
	return ret;		return ret;
	}		}

	if (pipe_config->dsc_params.compression_enable) {		if (pipe_config->dsc.compression_enable) {
	DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",		DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
	pipe_config->lane_count, pipe_config->port_clock,		pipe_config->lane_count, pipe_config->port_clock,
	pipe_config->pipe_bpp,		pipe_config->pipe_bpp,
	pipe_config->dsc_params.compressed_bpp);		pipe_config->dsc.compressed_bpp);

	DRM_DEBUG_KMS("DP link rate required %i available %i\n",		DRM_DEBUG_KMS("DP link rate required %i available %i\n",
	intel_dp_link_required(adjusted_mode->crtc_clock,		intel_dp_link_required(adjusted_mode->crtc_clock,
	pipe_config->dsc_params.compressed_bpp),		pipe_config->dsc.compressed_bpp),
	intel_dp_max_data_rate(pipe_config->port_clock,		intel_dp_max_data_rate(pipe_config->port_clock,
	pipe_config->lane_count));		pipe_config->lane_count));
	} else {		} else {
	@@ -2377,8 +2377,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
	pipe_config->limited_color_range =		pipe_config->limited_color_range =
	intel_dp_limited_color_range(pipe_config, conn_state);		intel_dp_limited_color_range(pipe_config, conn_state);

	if (pipe_config->dsc_params.compression_enable)		if (pipe_config->dsc.compression_enable)
	output_bpp = pipe_config->dsc_params.compressed_bpp;		output_bpp = pipe_config->dsc.compressed_bpp;
	else		else
	output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);		output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);

	@@ -3102,7 +3102,7 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
	{		{
	int ret;		int ret;

	if (!crtc_state->dsc_params.compression_enable)		if (!crtc_state->dsc.compression_enable)
	return;		return;

	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,

drivers/gpu/drm/i915/display/intel_psr.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -76,7 +76,7 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
	const struct intel_crtc_state *crtc_state)		const struct intel_crtc_state *crtc_state)
	{		{
	/* Cannot enable DSC and PSR2 simultaneously */		/* Cannot enable DSC and PSR2 simultaneously */
	WARN_ON(crtc_state->dsc_params.compression_enable &&		WARN_ON(crtc_state->dsc.compression_enable &&
	crtc_state->has_psr2);		crtc_state->has_psr2);

	switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {		switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
	@@ -623,7 +623,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
	* resolution requires DSC to be enabled, priority is given to DSC		* resolution requires DSC to be enabled, priority is given to DSC
	* over PSR2.		* over PSR2.
	*/		*/
	if (crtc_state->dsc_params.compression_enable) {		if (crtc_state->dsc.compression_enable) {
	DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");		DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
	return false;		return false;
	}		}

drivers/gpu/drm/i915/display/intel_vdsc.c

+34 −34

Original line number	Original line	Diff line number	Diff line
	@@ -323,7 +323,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
	struct intel_crtc_state *pipe_config)		struct intel_crtc_state *pipe_config)
	{		{
	struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg;		struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg;
	u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp;		u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
	u8 i = 0;		u8 i = 0;
	int row_index = 0;		int row_index = 0;
	int column_index = 0;		int column_index = 0;
	@@ -332,7 +332,7 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
	vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;		vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
	vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;		vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,		vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
	pipe_config->dsc_params.slice_count);		pipe_config->dsc.slice_count);
	/*		/*
	* Slice Height of 8 works for all currently available panels. So start		* Slice Height of 8 works for all currently available panels. So start
	* with that if pic_height is an integral multiple of 8.		* with that if pic_height is an integral multiple of 8.
	@@ -491,7 +491,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	u32 pps_val = 0;		u32 pps_val = 0;
	u32 rc_buf_thresh_dword[4];		u32 rc_buf_thresh_dword[4];
	u32 rc_range_params_dword[8];		u32 rc_range_params_dword[8];
	u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;		u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
	int i = 0;		int i = 0;

	/* Populate PICTURE_PARAMETER_SET_0 registers */		/* Populate PICTURE_PARAMETER_SET_0 registers */
	@@ -514,11 +514,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
	pps_val);		pps_val);
	}		}
	@@ -533,11 +533,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
	pps_val);		pps_val);
	}		}
	@@ -553,11 +553,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
	pps_val);		pps_val);
	}		}
	@@ -573,11 +573,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
	pps_val);		pps_val);
	}		}
	@@ -593,11 +593,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
	pps_val);		pps_val);
	}		}
	@@ -613,11 +613,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
	pps_val);		pps_val);
	}		}
	@@ -635,11 +635,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
	pps_val);		pps_val);
	}		}
	@@ -655,11 +655,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
	pps_val);		pps_val);
	}		}
	@@ -675,11 +675,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
	pps_val);		pps_val);
	}		}
	@@ -695,11 +695,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
	pps_val);		pps_val);
	}		}
	@@ -717,11 +717,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
	pps_val);		pps_val);
	}		}
	@@ -740,11 +740,11 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	* If 2 VDSC instances are needed, configure PPS for second		* If 2 VDSC instances are needed, configure PPS for second
	* VDSC		* VDSC
	*/		*/
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);		I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
	} else {		} else {
	I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);		I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
	if (crtc_state->dsc_params.dsc_split)		if (crtc_state->dsc.dsc_split)
	I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),		I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
	pps_val);		pps_val);
	}		}
	@@ -763,7 +763,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);		I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
	I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);		I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
	I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);		I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
	if (crtc_state->dsc_params.dsc_split) {		if (crtc_state->dsc.dsc_split) {
	I915_WRITE(DSCC_RC_BUF_THRESH_0,		I915_WRITE(DSCC_RC_BUF_THRESH_0,
	rc_buf_thresh_dword[0]);		rc_buf_thresh_dword[0]);
	I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,		I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
	@@ -782,7 +782,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	rc_buf_thresh_dword[2]);		rc_buf_thresh_dword[2]);
	I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),		I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
	rc_buf_thresh_dword[3]);		rc_buf_thresh_dword[3]);
	if (crtc_state->dsc_params.dsc_split) {		if (crtc_state->dsc.dsc_split) {
	I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),		I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
	rc_buf_thresh_dword[0]);		rc_buf_thresh_dword[0]);
	I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),		I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
	@@ -824,7 +824,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	rc_range_params_dword[6]);		rc_range_params_dword[6]);
	I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,		I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
	rc_range_params_dword[7]);		rc_range_params_dword[7]);
	if (crtc_state->dsc_params.dsc_split) {		if (crtc_state->dsc.dsc_split) {
	I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,		I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
	rc_range_params_dword[0]);		rc_range_params_dword[0]);
	I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,		I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
	@@ -859,7 +859,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
	rc_range_params_dword[6]);		rc_range_params_dword[6]);
	I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),		I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
	rc_range_params_dword[7]);		rc_range_params_dword[7]);
	if (crtc_state->dsc_params.dsc_split) {		if (crtc_state->dsc.dsc_split) {
	I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),		I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
	rc_range_params_dword[0]);		rc_range_params_dword[0]);
	I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),		I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
	@@ -909,7 +909,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
	u32 dss_ctl1_val = 0;		u32 dss_ctl1_val = 0;
	u32 dss_ctl2_val = 0;		u32 dss_ctl2_val = 0;

	if (!crtc_state->dsc_params.compression_enable)		if (!crtc_state->dsc.compression_enable)
	return;		return;

	/* Enable Power wells for VDSC/joining */		/* Enable Power wells for VDSC/joining */
	@@ -928,7 +928,7 @@ void intel_dsc_enable(struct intel_encoder *encoder,
	dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
	}		}
	dss_ctl2_val \|= LEFT_BRANCH_VDSC_ENABLE;		dss_ctl2_val \|= LEFT_BRANCH_VDSC_ENABLE;
	if (crtc_state->dsc_params.dsc_split) {		if (crtc_state->dsc.dsc_split) {
	dss_ctl2_val \|= RIGHT_BRANCH_VDSC_ENABLE;		dss_ctl2_val \|= RIGHT_BRANCH_VDSC_ENABLE;
	dss_ctl1_val \|= JOINER_ENABLE;		dss_ctl1_val \|= JOINER_ENABLE;
	}		}
	@@ -944,7 +944,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;		i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
	u32 dss_ctl1_val = 0, dss_ctl2_val = 0;		u32 dss_ctl1_val = 0, dss_ctl2_val = 0;

	if (!old_crtc_state->dsc_params.compression_enable)		if (!old_crtc_state->dsc.compression_enable)
	return;		return;

	if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {		if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {

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