Commit 00fe081d authored by William Wu's avatar William Wu Committed by Felipe Balbi
Browse files

usb: dwc3: add dis_del_phy_power_chg_quirk 



Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.

Signed-off-by: default avatarWilliam Wu <william.wu@rock-chips.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent 32f2ed86

Documentation/devicetree/bindings/usb/dwc3.txt

+2 −0
Original line number Diff line number Diff line
@@ -42,6 +42,8 @@ Optional properties: 
 - snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists

			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide

			a free-running PHY clock.

 - snps,dis-del-phy-power-chg-quirk: when set core will change PHY power

			from P0 to P1/P2/P3 without delay.

 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal

			utmi_l1_suspend_n, false when asserts utmi_sleep_n

 - snps,hird-threshold: HIRD threshold

drivers/usb/dwc3/core.c

+5 −0
Original line number Diff line number Diff line
@@ -448,6 +448,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc) 
	if (dwc->dis_u3_susphy_quirk)

		reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;



	if (dwc->dis_del_phy_power_chg_quirk)

		reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;



	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);



	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
@@ -947,6 +950,8 @@ static int dwc3_probe(struct platform_device *pdev) 
				"snps,dis_rxdet_inp3_quirk");

	dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,

				"snps,dis-u2-freeclk-exists-quirk");

	dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,

				"snps,dis-del-phy-power-chg-quirk");



	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,

				"snps,tx_de_emphasis_quirk");

drivers/usb/dwc3/core.h

+3 −0
Original line number Diff line number Diff line
@@ -818,6 +818,8 @@ struct dwc3_scratchpad_array { 
 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists

 *			in GUSB2PHYCFG, specify that USB2 PHY doesn't

 *			provide a free-running PHY clock.

 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power

 *			change quirk.

 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk

 * @tx_de_emphasis: Tx de-emphasis value

 * 	0	- -6dB de-emphasis
@@ -963,6 +965,7 @@ struct dwc3 { 
	unsigned		dis_enblslpm_quirk:1;

	unsigned		dis_rxdet_inp3_quirk:1;

	unsigned		dis_u2_freeclk_exists_quirk:1;

	unsigned		dis_del_phy_power_chg_quirk:1;



	unsigned		tx_de_emphasis_quirk:1;

	unsigned		tx_de_emphasis:2;

CRA Git | Maintained and supported by SUSTech CRA and CCSE