Commit 00f8ccd0 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'next/drivers' into next/late 



Merge in a few missing patches from the pull request (my copy of the
branch was behind the staged version in linux-next).

* next/drivers:
  memory: pl353: Add driver for arm pl353 static memory controller
  dt-bindings: memory: Add pl353 smc controller devicetree binding information
  firmware: qcom: scm: fix compilation error when disabled

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 8e564895 3e730e85

Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt

+8 −29
Original line number Diff line number Diff line
@@ -58,19 +58,11 @@ This binding for the SCU power domain providers uses the generic power 
domain binding[2].



Required properties:

- compatible:		Should be "fsl,scu-pd".

- #address-cells:	Should be 1.

- #size-cells:		Should be 0.



Required properties for power domain sub nodes:

- #power-domain-cells:	Must be 0.



Optional Properties:

- reg:			Resource ID of this power domain.

			No exist means uncontrollable by user.

- compatible:		Should be "fsl,imx8qxp-scu-pd".

- #power-domain-cells:	Must be 1. Contains the Resource ID used by

			SCU commands.

			See detailed Resource ID list from:

			include/dt-bindings/power/imx-rsrc.h

- power-domains:	phandle pointing to the parent power domain.

			include/dt-bindings/firmware/imx/rsrc.h



Clock bindings based on SCU Message Protocol

------------------------------------------------------------
@@ -152,22 +144,9 @@ firmware { 
			...

		};



		imx8qx-pm {

			compatible = "fsl,scu-pd";

			#address-cells = <1>;

			#size-cells = <0>;



			pd_dma: dma-power-domain {

				#power-domain-cells = <0>;



				pd_dma_lpuart0: dma-lpuart0@57 {

					reg = <SC_R_UART_0>;

					#power-domain-cells = <0>;

					power-domains = <&pd_dma>;

				};

				...

			};

			...

		pd: imx8qx-pd {

			compatible = "fsl,imx8qxp-scu-pd";

			#power-domain-cells = <1>;

		};

	};

};
@@ -179,5 +158,5 @@ serial@5a060000 { 
	clocks = <&clk IMX8QXP_UART0_CLK>,

		 <&clk IMX8QXP_UART0_IPG_CLK>;

	clock-names = "per", "ipg";

	power-domains = <&pd_dma_lpuart0>;

	power-domains = <&pd IMX_SC_R_UART_0>;

};

Documentation/devicetree/bindings/bus/ti-sysc.txt

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ Required standard properties: 
		"ti,sysc-omap3-sham"

		"ti,sysc-omap-aes"

		"ti,sysc-mcasp"

		"ti,sysc-dra7-mcasp"

		"ti,sysc-usb-host-fs"

		"ti,sysc-dra7-mcan"

Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt

0 → 100644
+47 −0
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Device tree bindings for ARM PL353 static memory controller



PL353 static memory controller supports two kinds of memory

interfaces.i.e NAND and SRAM/NOR interfaces.

The actual devices are instantiated from the child nodes of pl353 smc node.



Required properties:

- compatible		: Should be "arm,pl353-smc-r2p1", "arm,primecell".

- reg			: Controller registers map and length.

- clock-names		: List of input clock names - "memclk", "apb_pclk"

			  (See clock bindings for details).

- clocks		: Clock phandles (see clock bindings for details).

- address-cells		: Must be 2.

- size-cells		: Must be 1.



Child nodes:

 For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are

supported as child nodes.



for NAND partition information please refer the below file

Documentation/devicetree/bindings/mtd/partition.txt



Example:

	smcc: memory-controller@e000e000

			compatible = "arm,pl353-smc-r2p1", "arm,primecell";

			clock-names = "memclk", "apb_pclk";

			clocks = <&clkc 11>, <&clkc 44>;

			reg = <0xe000e000 0x1000>;

			#address-cells = <2>;

			#size-cells = <1>;

			ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region

				  0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region

				  0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region

			nand_0: flash@e1000000 {

				compatible = "arm,pl353-nand-r2p1"

				reg = <0 0 0x1000000>;

				(...)

			};

			nor0: flash@e2000000 {

				compatible = "cfi-flash";

				reg = <1 0 0x2000000>;

			};

			nor1: flash@e4000000 {

				compatible = "cfi-flash";

				reg = <2 0 0x2000000>;

			};

	};

Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt

+5 −2
Original line number Diff line number Diff line
@@ -6,7 +6,9 @@ Control (PGC) for various power domains. 


Required properties:



- compatible: Should be "fsl,imx7d-gpc"

- compatible: Should be one of:

	- "fsl,imx7d-gpc"

	- "fsl,imx8mq-gpc"



- reg: should be register base and length as documented in the

  datasheet
@@ -22,7 +24,8 @@ which, in turn, is expected to contain the following: 
Required properties:



- reg: Power domain index. Valid values are defined in

  include/dt-bindings/power/imx7-power.h

  include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and

  include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc



- #power-domain-cells: Should be 0

Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt

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+18 −0
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Amlogic Internal Clock Measurer

===============================



The Amlogic SoCs contains an IP to measure the internal clocks.

The precision is multiple of MHz, useful to debug the clock states.



Required properties:

- compatible: Shall contain one of the following :

			"amlogic,meson-gx-clk-measure" for GX SoCs

			"amlogic,meson8-clk-measure" for Meson8 SoCs

			"amlogic,meson8b-clk-measure" for Meson8b SoCs

- reg: base address and size of the Clock Measurer register space.



Example:

	clock-measure@8758 {

		compatible = "amlogic,meson-gx-clk-measure";

		reg = <0x0 0x8758 0x0 0x10>;

	};

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