Commit 00e3d2ef authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'wireless-drivers-next-for-davem-2016-03-09' of... 

Merge tag 'wireless-drivers-next-for-davem-2016-03-09' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next



Kalle Valo says:

====================
wireless-drivers patches for 4.6

Major changes:

ath10k

* dt: add bindings for ipq4019 wifi block
* start adding support for qca4019 chip

ath9k

* add device ID for Toshiba WLM-20U2/GN-1080
* allow more than one interface on DFS channels

bcma

* move flash detection code to ChipCommon core driver

brcmfmac

* IPv6 Neighbor discovery offload
* driver settings that can be populated from different sources
* country code setting in firmware
* length checks to validate firmware events
* new way to determine device memory size needed for BCM4366
* various offloads during Wake on Wireless LAN (WoWLAN)
* full Management Frame Protection (MFP) support

iwlwifi

* add support for thermal device / cooling device
* improvements in scheduled scan without profiles
* new firmware support (-21.ucode)
* add MSIX support for 9000 devices
* enable MU-MIMO and take care of firmware restart
* add support for large SKBs in mvm to reach A-MSDU
* add support for filtering frames from a BA session
* start implementing the new Rx path for 9000 devices
* enable the new Radio Resource Management (RRM) nl80211 feature flag
* add a new module paramater to disable VHT
* build infrastructure for Dynamic Queue Allocation
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents f22f5f60 836856e3

Documentation/devicetree/bindings/net/wireless/qcom,ath10k.txt

+84 −5
Original line number Original line Diff line number Diff line 
* Qualcomm Atheros ath10k wireless devices

* Qualcomm Atheros ath10k wireless devices





For ath10k devices the calibration data can be provided through Device

Tree. The node is a child node of the PCI controller.



Required properties:

Required properties:

-compatible : Should be "qcom,ath10k"

- compatible: Should be one of the following:

	* "qcom,ath10k"

	* "qcom,ipq4019-wifi"



PCI based devices uses compatible string "qcom,ath10k" and takes only

calibration data via "qcom,ath10k-calibration-data". Rest of the properties

are not applicable for PCI based devices.



AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"

and also uses most of the properties defined in this doc.





Optional properties:

Optional properties:

- reg: Address and length of the register set for the device.

- resets: Must contain an entry for each entry in reset-names.

          See ../reset/reseti.txt for details.

- reset-names: Must include the list of following reset names,

	       "wifi_cpu_init"

	       "wifi_radio_srif"

	       "wifi_radio_warm"

	       "wifi_radio_cold"

	       "wifi_core_warm"

	       "wifi_core_cold"

- clocks: List of clock specifiers, must contain an entry for each required

          entry in clock-names.

- clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref",

               "wifi_wcss_rtc".

- interrupts: List of interrupt lines. Must contain an entry

	      for each entry in the interrupt-names property.

- interrupt-names: Must include the entries for MSI interrupt

		   names ("msi0" to "msi15") and legacy interrupt

		   name ("legacy"),

- qcom,msi_addr: MSI interrupt address.

- qcom,msi_base: Base value to add before writing MSI data into

		MSI address register.

- qcom,ath10k-calibration-data : calibration data as an array, the

- qcom,ath10k-calibration-data : calibration data as an array, the

				 length can vary between hw versions

				 length can vary between hw versions





Example (to supply the calibration data alone):





Example:

In this example, the node is defined as child node of the PCI controller.





pci {

pci {

	pcie@0 {

	pcie@0 {
@@ -28,3 +57,53 @@ pci { 
		};

		};

	};

	};

};

};



Example (to supply ipq4019 SoC wifi block details):



wifi0: wifi@a000000 {

	compatible = "qcom,ipq4019-wifi";

	reg = <0xa000000 0x200000>;

	resets = <&gcc WIFI0_CPU_INIT_RESET>,

		 <&gcc WIFI0_RADIO_SRIF_RESET>,

		 <&gcc WIFI0_RADIO_WARM_RESET>,

		 <&gcc WIFI0_RADIO_COLD_RESET>,

		 <&gcc WIFI0_CORE_WARM_RESET>,

		 <&gcc WIFI0_CORE_COLD_RESET>;

	reset-names = "wifi_cpu_init",

		      "wifi_radio_srif",

		      "wifi_radio_warm",

		      "wifi_radio_cold",

		      "wifi_core_warm",

		      "wifi_core_cold";

	clocks = <&gcc GCC_WCSS2G_CLK>,

		 <&gcc GCC_WCSS2G_REF_CLK>,

		 <&gcc GCC_WCSS2G_RTC_CLK>;

	clock-names = "wifi_wcss_cmd",

		      "wifi_wcss_ref",

		      "wifi_wcss_rtc";

	interrupts = <0 0x20 0x1>,

		     <0 0x21 0x1>,

		     <0 0x22 0x1>,

		     <0 0x23 0x1>,

		     <0 0x24 0x1>,

		     <0 0x25 0x1>,

		     <0 0x26 0x1>,

		     <0 0x27 0x1>,

		     <0 0x28 0x1>,

		     <0 0x29 0x1>,

		     <0 0x2a 0x1>,

		     <0 0x2b 0x1>,

		     <0 0x2c 0x1>,

		     <0 0x2d 0x1>,

		     <0 0x2e 0x1>,

		     <0 0x2f 0x1>,

		     <0 0xa8 0x0>;

	interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",

			  "msi4",  "msi5",  "msi6",  "msi7",

			  "msi8",  "msi9",  "msi10", "msi11",

			  "msi12", "msi13", "msi14", "msi15",

			  "legacy";

	qcom,msi_addr = <0x0b006040>;

	qcom,msi_base = <0x40>;

	qcom,ath10k-calibration-data = [ 01 02 03 ... ];

};

drivers/bcma/Kconfig

+5 −0
Original line number Original line Diff line number Diff line
@@ -70,6 +70,11 @@ config BCMA_DRIVER_MIPS 




	  If unsure, say N

	  If unsure, say N





config BCMA_PFLASH

	bool

	depends on BCMA_DRIVER_MIPS

	default y



config BCMA_SFLASH

config BCMA_SFLASH

	bool

	bool

	depends on BCMA_DRIVER_MIPS

	depends on BCMA_DRIVER_MIPS

drivers/bcma/Makefile

+1 −0
Original line number Original line Diff line number Diff line 
bcma-y					+= main.o scan.o core.o sprom.o

bcma-y					+= main.o scan.o core.o sprom.o

bcma-y					+= driver_chipcommon.o driver_chipcommon_pmu.o

bcma-y					+= driver_chipcommon.o driver_chipcommon_pmu.o

bcma-y					+= driver_chipcommon_b.o

bcma-y					+= driver_chipcommon_b.o

bcma-$(CONFIG_BCMA_PFLASH)		+= driver_chipcommon_pflash.o

bcma-$(CONFIG_BCMA_SFLASH)		+= driver_chipcommon_sflash.o

bcma-$(CONFIG_BCMA_SFLASH)		+= driver_chipcommon_sflash.o

bcma-$(CONFIG_BCMA_NFLASH)		+= driver_chipcommon_nflash.o

bcma-$(CONFIG_BCMA_NFLASH)		+= driver_chipcommon_nflash.o

bcma-$(CONFIG_BCMA_DRIVER_PCI)		+= driver_pci.o

bcma-$(CONFIG_BCMA_DRIVER_PCI)		+= driver_pci.o

drivers/bcma/bcma_private.h

+15 −3
Original line number Original line Diff line number Diff line
@@ -47,9 +47,6 @@ int bcma_sprom_get(struct bcma_bus *bus); 
void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);

void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);

void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);

void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);

void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);

void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);

#ifdef CONFIG_BCMA_DRIVER_MIPS

extern struct platform_device bcma_pflash_dev;

#endif /* CONFIG_BCMA_DRIVER_MIPS */





/* driver_chipcommon_b.c */

/* driver_chipcommon_b.c */

int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);

int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
@@ -61,6 +58,21 @@ void bcma_pmu_init(struct bcma_drv_cc *cc); 
u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);

u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);

u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);

u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);





/**************************************************

 * driver_chipcommon_sflash.c

 **************************************************/



#ifdef CONFIG_BCMA_PFLASH

extern struct platform_device bcma_pflash_dev;

int bcma_pflash_init(struct bcma_drv_cc *cc);

#else

static inline int bcma_pflash_init(struct bcma_drv_cc *cc)

{

	bcma_err(cc->core->bus, "Parallel flash not supported\n");

	return 0;

}

#endif /* CONFIG_BCMA_PFLASH */



#ifdef CONFIG_BCMA_SFLASH

#ifdef CONFIG_BCMA_SFLASH

/* driver_chipcommon_sflash.c */

/* driver_chipcommon_sflash.c */

int bcma_sflash_init(struct bcma_drv_cc *cc);

int bcma_sflash_init(struct bcma_drv_cc *cc);

drivers/bcma/driver_chipcommon.c

+30 −0
Original line number Original line Diff line number Diff line
@@ -115,6 +115,33 @@ int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc) 
	return 0;

	return 0;

}

}





static void bcma_core_chipcommon_flash_detect(struct bcma_drv_cc *cc)

{

	struct bcma_bus *bus = cc->core->bus;



	switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {

	case BCMA_CC_FLASHT_STSER:

	case BCMA_CC_FLASHT_ATSER:

		bcma_debug(bus, "Found serial flash\n");

		bcma_sflash_init(cc);

		break;

	case BCMA_CC_FLASHT_PARA:

		bcma_debug(bus, "Found parallel flash\n");

		bcma_pflash_init(cc);

		break;

	default:

		bcma_err(bus, "Flash type not supported\n");

	}



	if (cc->core->id.rev == 38 ||

	    bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {

		if (cc->capabilities & BCMA_CC_CAP_NFLASH) {

			bcma_debug(bus, "Found NAND flash\n");

			bcma_nflash_init(cc);

		}

	}

}



void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)

void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)

{

{

	struct bcma_bus *bus = cc->core->bus;

	struct bcma_bus *bus = cc->core->bus;
@@ -136,6 +163,9 @@ void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) 
	if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)

	if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)

		bcma_chipco_serial_init(cc);

		bcma_chipco_serial_init(cc);





	if (bus->hosttype == BCMA_HOSTTYPE_SOC)

		bcma_core_chipcommon_flash_detect(cc);



	cc->early_setup_done = true;

	cc->early_setup_done = true;

}

}

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