Commit 00e1e623 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Init some CHV workarounds via LRIs in ring->init_context() 



Follow the BDW example and apply the workarounds touching registers
which are saved in the context image through LRIs in the new
ring->init_context() hook.

This makes Mesa much happier and eg. glxgears doesn't hang after
the first frame.

Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Add missing wa table initialization to avoid a functional
conflict with Arun's wa table debugfs support.]
Reviewed-by: default avatar"Barbalho, Rafael" <rafael.barbalho@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 21386f86

drivers/gpu/drm/i915/intel_pm.c

+0 −14
Original line number Diff line number Diff line
@@ -6011,14 +6011,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev) 


	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);



	/* WaDisablePartialInstShootdown:chv */

	I915_WRITE(GEN8_ROW_CHICKEN,

		   _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));



	/* WaDisableThreadStallDopClockGating:chv */

	I915_WRITE(GEN8_ROW_CHICKEN,

		   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));



	/* WaVSRefCountFullforceMissDisable:chv */

	/* WaDSRefCountFullforceMissDisable:chv */

	I915_WRITE(GEN7_FF_THREAD_MODE,
@@ -6037,10 +6029,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev) 
	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |

		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);



	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */

	I915_WRITE(HALF_SLICE_CHICKEN3,

		   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));



	/* WaDisableGunitClockGating:chv (pre-production hw) */

	I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |

		   GINT_DIS);
@@ -6050,8 +6038,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev) 
		   _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));



	/* WaDisableDopClockGating:chv (pre-production hw) */

	I915_WRITE(GEN7_ROW_CHICKEN2,

		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));

	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |

		   GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);

}

drivers/gpu/drm/i915/intel_ringbuffer.c

+44 −2
Original line number Diff line number Diff line
@@ -681,7 +681,7 @@ static inline void intel_ring_emit_wa(struct intel_engine_cs *ring, 
	return;

}



static int gen8_init_workarounds(struct intel_engine_cs *ring)

static int bdw_init_workarounds(struct intel_engine_cs *ring)

{

	int ret;

	struct drm_device *dev = ring->dev;
@@ -758,6 +758,45 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring) 
	return 0;

}



static int chv_init_workarounds(struct intel_engine_cs *ring)

{

	int ret;

	struct drm_device *dev = ring->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;



	/*

	 * workarounds applied in this fn are part of register state context,

	 * they need to be re-initialized followed by gpu reset, suspend/resume,

	 * module reload.

	 */

	dev_priv->num_wa_regs = 0;

	memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));



	ret = intel_ring_begin(ring, 12);

	if (ret)

		return ret;



	/* WaDisablePartialInstShootdown:chv */

	intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,

			   _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));



	/* WaDisableThreadStallDopClockGating:chv */

	intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,

			   _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));



	/* WaDisableDopClockGating:chv (pre-production hw) */

	intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,

			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));



	/* WaDisableSamplerPowerBypass:chv (pre-production hw) */

	intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,

			   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));



	intel_ring_advance(ring);



	return 0;

}



static int init_render_ring(struct intel_engine_cs *ring)

{

	struct drm_device *dev = ring->dev;
@@ -2244,7 +2283,10 @@ int intel_init_render_ring_buffer(struct drm_device *dev) 
					dev_priv->semaphore_obj = obj;

			}

		}

		ring->init_context = gen8_init_workarounds;

		if (IS_CHERRYVIEW(dev))

			ring->init_context = chv_init_workarounds;

		else

			ring->init_context = bdw_init_workarounds;

		ring->add_request = gen6_add_request;

		ring->flush = gen8_render_ring_flush;

		ring->irq_get = gen8_ring_get_irq;

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