Commit 00c5ce8a authored by Ran Wang's avatar Ran Wang Committed by Shawn Guo
Browse files

arm64: dts: lx2160a: add cpu idle support 



lx2160a supports pw20 which could help save more power during cpu is
dile. It needs system firmware support via PSCI.

Signed-off-by: default avatarRan Wang <ran.wang_1@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent ade5a57e

arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster0_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@1 {
@@ -48,6 +49,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster0_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@100 {
@@ -63,6 +65,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster1_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@101 {
@@ -78,6 +81,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster1_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@200 {
@@ -93,6 +97,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster2_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@201 {
@@ -108,6 +113,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster2_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@300 {
@@ -123,6 +129,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster3_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@301 {
@@ -138,6 +145,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster3_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@400 {
@@ -153,6 +161,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster4_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@401 {
@@ -168,6 +177,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster4_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@500 {
@@ -183,6 +193,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster5_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@501 {
@@ -198,6 +209,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster5_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@600 {
@@ -213,6 +225,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster6_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@601 {
@@ -228,6 +241,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster6_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@700 {
@@ -243,6 +257,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster7_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cpu@701 {
@@ -258,6 +273,7 @@ 
			i-cache-line-size = <64>;

			i-cache-sets = <192>;

			next-level-cache = <&cluster7_l2>;

			cpu-idle-states = <&cpu_pw20>;

		};



		cluster0_l2: l2-cache0 {
@@ -323,6 +339,15 @@ 
			cache-sets = <1024>;

			cache-level = <2>;

		};



		cpu_pw20: cpu-pw20 {

			compatible = "arm,idle-state";

			idle-state-name = "PW20";

			arm,psci-suspend-param = <0x0>;

			entry-latency-us = <2000>;

			exit-latency-us = <2000>;

			min-residency-us = <6000>;

		  };

	};



	gic: interrupt-controller@6000000 {

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