Commit 00c5a926 authored by Chris Packham's avatar Chris Packham Committed by Stephen Boyd
Browse files

clk: mvebu: use correct bit for 98DX3236 NAND 



The correct fieldbit value for the NAND PLL reload trigger is 27.

Fixes: commit e120c17a ("clk: mvebu: support for 98DX3236 SoC")
Signed-off-by: default avatarChris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 60cc43fc

drivers/clk/mvebu/clk-corediv.c

+1 −1
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = { 
};



static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {

	{ .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */

	{ .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */

};



#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)

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