Commit 00bb485c authored by Mathieu Poirier's avatar Mathieu Poirier Committed by Greg Kroah-Hartman
Browse files

coresight: tmc: Make memory width mask computation into a function 



Make the computation of a memory mask representing the width of the memory
bus into a function so that it can be re-used by the ETR driver.

Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: default avatarLeo Yan <leo.yan@linaro.org>
Link: https://lore.kernel.org/r/20190829202842.580-16-mathieu.poirier@linaro.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent bbedcb91

drivers/hwtracing/coresight/coresight-tmc-etf.c

+2 −21
Original line number Diff line number Diff line
@@ -479,30 +479,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, 
	 * traces.

	 */

	if (!buf->snapshot && to_read > handle->size) {

		u32 mask = 0;



		/*

		 * The value written to RRP must be byte-address aligned to

		 * the width of the trace memory databus _and_ to a frame

		 * boundary (16 byte), whichever is the biggest. For example,

		 * for 32-bit, 64-bit and 128-bit wide trace memory, the four

		 * LSBs must be 0s. For 256-bit wide trace memory, the five

		 * LSBs must be 0s.

		 */

		switch (drvdata->memwidth) {

		case TMC_MEM_INTF_WIDTH_32BITS:

		case TMC_MEM_INTF_WIDTH_64BITS:

		case TMC_MEM_INTF_WIDTH_128BITS:

			mask = GENMASK(31, 4);

			break;

		case TMC_MEM_INTF_WIDTH_256BITS:

			mask = GENMASK(31, 5);

			break;

		}

		u32 mask = tmc_get_memwidth_mask(drvdata);



		/*

		 * Make sure the new size is aligned in accordance with the

		 * requirement explained above.

		 * requirement explained in function tmc_get_memwidth_mask().

		 */

		to_read = handle->size & mask;

		/* Move the RAM read pointer up */

drivers/hwtracing/coresight/coresight-tmc.c

+28 −0
Original line number Diff line number Diff line
@@ -70,6 +70,34 @@ void tmc_disable_hw(struct tmc_drvdata *drvdata) 
	writel_relaxed(0x0, drvdata->base + TMC_CTL);

}



u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata)

{

	u32 mask = 0;



	/*

	 * When moving RRP or an offset address forward, the new values must

	 * be byte-address aligned to the width of the trace memory databus

	 * _and_ to a frame boundary (16 byte), whichever is the biggest. For

	 * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four

	 * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must

	 * be 0s.

	 */

	switch (drvdata->memwidth) {

	case TMC_MEM_INTF_WIDTH_32BITS:

	/* fallthrough */

	case TMC_MEM_INTF_WIDTH_64BITS:

	/* fallthrough */

	case TMC_MEM_INTF_WIDTH_128BITS:

		mask = GENMASK(31, 4);

		break;

	case TMC_MEM_INTF_WIDTH_256BITS:

		mask = GENMASK(31, 5);

		break;

	}



	return mask;

}



static int tmc_read_prepare(struct tmc_drvdata *drvdata)

{

	int ret = 0;

drivers/hwtracing/coresight/coresight-tmc.h

+1 −0
Original line number Diff line number Diff line
@@ -255,6 +255,7 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); 
void tmc_flush_and_stop(struct tmc_drvdata *drvdata);

void tmc_enable_hw(struct tmc_drvdata *drvdata);

void tmc_disable_hw(struct tmc_drvdata *drvdata);

u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);



/* ETB/ETF functions */

int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);

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