PCI: keystone: Use quirk to set MRRS for PCI host bridge (00a2c409) · Commits · 戴 / test

drivers/pci/controller/dwc/pci-keystone.c

+15 −22

Original line number	Diff line number	Diff line
		@@ -43,7 +43,7 @@
		static void quirk_limit_mrrs(struct pci_dev *dev)
		{
		struct pci_bus *bus = dev->bus;
		struct pci_dev *bridge = bus->self;
		struct pci_dev *bridge;
		static const struct pci_device_id rc_pci_devids[] = {
		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
		.class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
		@@ -57,7 +57,7 @@ static void quirk_limit_mrrs(struct pci_dev *dev)
		};

		if (pci_is_root_bus(bus))
		return;
		bridge = dev;

		/* look for the host bridge */
		while (!pci_is_root_bus(bus)) {
		@@ -65,7 +65,9 @@ static void quirk_limit_mrrs(struct pci_dev *dev)
		bus = bus->parent;
		}

		if (bridge) {
		if (!bridge)
		return;

		/*
		* Keystone PCI controller has a h/w limitation of
		* 256 bytes maximum read request size. It can't handle
		@@ -79,7 +81,6 @@ static void quirk_limit_mrrs(struct pci_dev *dev)
		}
		}
		}
		}
		DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);

		static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
		@@ -264,7 +265,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
		{
		struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
		struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
		u32 val;

		ks_pcie_establish_link(ks_pcie);
		ks_dw_pcie_setup_rc_app_regs(ks_pcie);
		@@ -275,13 +275,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
		/* update the Vendor ID */
		writew(ks_pcie->device_id, pci->dbi_base + PCI_DEVICE_ID);

		/* update the DEV_STAT_CTRL to publish right mrrs */
		val = readl(pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
		val &= ~PCI_EXP_DEVCTL_READRQ;
		/* set the mrrs to 256 bytes */
		val \|= BIT(12);
		writel(val, pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);

		/*
		* PCIe access errors that result into OCP errors are caught by ARM as
		* "External aborts"

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