Commit fc9d39a0 authored by Hoang Nguyen's avatar Hoang Nguyen Committed by Benjamin Cabé
Browse files

soc: renesas: Add support for Renesas RZ/N2L



Add support for Renesas RZ/N2L

Signed-off-by: default avatarHoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: default avatarNhut Nguyen <nhut.nguyen.kc@renesas.com>
parent fa82af24
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/*
 * Copyright (c) 2025 Renesas Electronics Corporation
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <arm/armv8-r.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "renesas,r9a07g084";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <0>;
		};
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
	};

	soc {
		interrupt-parent = <&gic>;

		gic: interrupt-controller@94000000 {
			compatible = "arm,gic-v3", "arm,gic";
			reg = <0x94000000 0x10000>,
				<0x94100000 0x80000>;
			interrupt-controller;
			#interrupt-cells = <4>;
			status = "okay";
		};

		atcm: memory@0 {
			compatible = "mmio-sram";
			reg = <0x00000000 DT_SIZE_K(128)>;
		};

		btcm: memory@100000 {
			compatible = "mmio-sram";
			reg = <0x00100000 DT_SIZE_K(128)>;
		};

		sram: memory@10000000 {
			compatible = "mmio-sram";
			reg = <0x10000000 (DT_SIZE_M(1) + DT_SIZE_K(512))>;
		};

		xspi0_cs0: memory@60000000 {
			compatible = "mmio-sram";
			reg = <0x60000000 DT_SIZE_M(64)>;

			partitions {
				compatible = "fixed-partitions";
				#address-cells = <1>;
				#size-cells = <1>;

				loader_param: partition@0 {
					label = "loader-param";
					reg = <0x00000000 0x4C>;
					read-only;
				};

				loader_program: partition@4C {
					label = "loader-program";
					reg = <0x0000004C (DT_SIZE_K(56) - 0x4C)>;
					read-only;
				};

				slot0_partition: partition@E000 {
					label = "image-0";
					reg = <0x0000E000 (DT_SIZE_M(64) - DT_SIZE_K(56))>;
					read-only;
				};
			};
		};
	};
};
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/*
 * Copyright (c) 2025 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/devicetree.h>
#include <zephyr/linker/sections.h>

#define ROM_START	(CONFIG_FLASH_BASE_ADDRESS + DT_REG_ADDR(DT_CHOSEN(zephyr_code_partition)))
#define RAM_START	_image_ram_start // Require CONFIG_XIP=n
#define APP_SIZE	_image_ram_size

_ASM_FILE_PROLOGUE

GTEXT(loader_program)

/*
 * Loader program
 */
SECTION_FUNC(loader_text, loader_program)
	ldr r0, =ROM_START         // Src in ROM
	ldr r1, =RAM_START         // Des in RAM
	ldr r2, =APP_SIZE

	cmp r2, #0
	beq exit

loop:
	ldrb r3, [r0], #1    // Load byte from src and increment src pointer
	strb r3, [r1], #1    // Store byte to des and increment des pointer
	subs r2, r2, #1      // Decrement size and updates the condition flags
	bne loop             // If size is not 0, repeat loop

done:
	dsb sy
	ldr pc, =__start

exit:
	wfi
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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0

zephyr_sources(
  soc.c
  loader_param.c
  ../common/loader_program.S
)

zephyr_include_directories(.)

zephyr_linker_sources(SECTIONS sections.ld)

set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "")
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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_RZN2L
	select ARM
	select CPU_CORTEX_R52
	select CPU_HAS_ARM_MPU
	select HAS_RENESAS_RZ_FSP
	select ARM_ARCH_TIMER
	select GIC_SINGLE_SECURITY_STATE
	select SOC_RESET_HOOK
	select SOC_EARLY_INIT_HOOK
	select ARM_CUSTOM_INTERRUPT_CONTROLLER
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# Copyright (c) 2025 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0

if SOC_SERIES_RZN2L

config NUM_IRQS
	default 480

config SYS_CLOCK_HW_CYCLES_PER_SEC
	default 25000000

config FPU
	default y

config FLASH_SIZE
	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)

config FLASH_BASE_ADDRESS
	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))

DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition

config BUILD_OUTPUT_ADJUST_LMA
	default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) + \
	$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)))"

config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
	default "*;!.loader"

endif # SOC_SERIES_RZN2L
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