drivers: clock_control: Add condition to verify the CPU clock config (fc831ead) · Commits · Wenxi XU / zephyr

boards/renesas/ek_ra4w1/ek_ra4w1_defconfig

+1 −1

Changes for boards/renesas/ek_ra4w1/ek_ra4w1_defconfig: 1 added line, 1 removed line.
Original line number	Diff line number	Diff line
		# Copyright (c) 2024 Renesas Electronics Corporation
		# SPDX-License-Identifier: Apache-2.0

		CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
		CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000

		# Enable GPIO
		CONFIG_GPIO=y

+14 −0

Changes for drivers/clock_control/clock_control_renesas_ra_cgc.c: 14 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		@@ -23,6 +23,20 @@ static volatile uint32_t *mstp_regs[] = {
		static volatile uint32_t *mstp_regs[] = {};
		#endif

		#if !defined(CONFIG_PM)
		/* If a CPU clock exists in the system, it will be the source for the CPU */
		#if BSP_FEATURE_CGC_HAS_CPUCLK
		#define sys_clk DT_NODELABEL(cpuclk)
		#else
		#define sys_clk DT_NODELABEL(iclk)
		#endif

		#define SYS_CLOCK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / DT_PROP(sys_clk, div))

		BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == SYS_CLOCK_HZ,
		"CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC must match the configuration of the clock "
		"supplying the CPU ");
		#endif
		static int clock_control_renesas_ra_on(const struct device *dev, clock_control_subsys_t sys)
		{
		struct clock_control_ra_subsys_cfg subsys_clk = (struct clock_control_ra_subsys_cfg )sys;