Commit f989ed94 authored by Jimmy Zheng's avatar Jimmy Zheng Committed by Anas Nashif
Browse files

driver: interrupt_controller: nuclei_eclic: fixed interrupt level 



CLIC should be the first level interrupt controller because it replaces
the basic RISC-V local interrupt.
The interrupt level in CLIC controls preemption between IRQs, rather than
specifying the number of nested interrupt controllers.
Removed CONFIG_MULTI_LEVEL_INTERRUPTS and the incorrect interrupt level.

Signed-off-by: default avatarJimmy Zheng <jimmyzhe@andestech.com>
parent ee69e9fa

drivers/interrupt_controller/Kconfig.clic

+0 −1
Original line number Diff line number Diff line
@@ -5,7 +5,6 @@ config NUCLEI_ECLIC 
	bool "Enhanced Core Local Interrupt Controller (ECLIC)"

	default y

	depends on DT_HAS_NUCLEI_ECLIC_ENABLED

	select MULTI_LEVEL_INTERRUPTS

	select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING if !RISCV_VECTORED_MODE

	help

	  Interrupt controller for Nuclei SoC core.

drivers/interrupt_controller/intc_nuclei_eclic.c

+2 −14
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ 
#include <zephyr/arch/cpu.h>

#include <zephyr/sys/util.h>

#include <zephyr/device.h>

#include <zephyr/irq_multilevel.h>



#include <zephyr/sw_isr_table.h>

#include <zephyr/drivers/interrupt_controller/riscv_clic.h>
@@ -96,14 +95,6 @@ struct CLICCTRL { 
#define ECLIC_CTRL      ((volatile  struct CLICCTRL *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 3)))

#define ECLIC_CTRL_SIZE (DT_REG_SIZE_BY_IDX(DT_NODELABEL(eclic), 3))



#if CONFIG_3RD_LEVEL_INTERRUPTS

#define INTERRUPT_LEVEL 2

#elif CONFIG_2ND_LEVEL_INTERRUPTS

#define INTERRUPT_LEVEL 1

#else

#define INTERRUPT_LEVEL 0

#endif



static uint8_t nlbits;

static uint8_t intctlbits;

static uint8_t max_prio;
@@ -150,7 +141,7 @@ int riscv_clic_irq_is_enabled(uint32_t irq) 
void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)

{

	const uint8_t prio = leftalign8(MIN(pri, max_prio), intctlbits);

	const uint8_t level =  leftalign8(MIN((irq_get_level(irq) - 1), max_level), nlbits);

	const uint8_t level =  leftalign8(max_level, nlbits);

	const uint8_t intctrl = (prio | level) | (~intctrl_mask);



	ECLIC_CTRL[irq].INTCTRL = intctrl;
@@ -180,12 +171,9 @@ void riscv_clic_irq_set_pending(uint32_t irq) 


static int nuclei_eclic_init(const struct device *dev)

{

	/* check hardware support required interrupt levels */

	__ASSERT_NO_MSG(ECLIC_INFO.b.intctlbits >= INTERRUPT_LEVEL);



	ECLIC_MTH.w = 0;

	ECLIC_CFG.w = 0;

	ECLIC_CFG.b.nlbits = INTERRUPT_LEVEL;

	ECLIC_CFG.b.nlbits = 0;

	for (int i = 0; i < ECLIC_CTRL_SIZE; i++) {

		ECLIC_CTRL[i] = (struct CLICCTRL) { 0 };

	}

soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103

+0 −3
Original line number Diff line number Diff line
@@ -24,9 +24,6 @@ config NUM_IRQS 
	default 87 if  NUCLEI_ECLIC

	default 16 if !NUCLEI_ECLIC



config 2ND_LEVEL_INTERRUPTS

	default y



config ARCH_IRQ_VECTOR_TABLE_ALIGN

	default 512 if NUCLEI_ECLIC

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