Skip to content
Commit f8e812aa authored by Brett Witherspoon's avatar Brett Witherspoon Committed by Carles Cufí
Browse files

dts: arm: st: u5: correct lptim2 clock enable bit 



The LPTIM2 clock enable is bit 5 of RCC APB1 clock enable register 2
(RM0456 Rev 4 11.8.34).

Signed-off-by: default avatarBrett Witherspoon <brett@witherspoon.engineering>
parent 29f6ea43
Show whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please to comment

CRA Git | Maintained and supported by SUSTech CRA and CCSE