Commit f67b3216 authored by Camille BAUD's avatar Camille BAUD Committed by Benjamin Cabé
Browse files

soc: Introduce Qingke V4C-based CH32V208 SoC 



This introduces the only CH32 Serie Qingke V4C SoC, CH32V208

Signed-off-by: default avatarCamille BAUD <mail@massdriver.space>
parent 55a3e606

dts/bindings/cpu/wch,qingke-v4c.yaml

0 → 100644
+8 −0
Original line number Diff line number Diff line 
# Copyright (c) 2024 MASSDRIVER EI (massdriver.space)

# SPDX-License-Identifier: Apache-2.0



description: WCH QingKe V4C RISC-V MCU



compatible: "wch,qingke-v4c"



include: riscv,cpus.yaml

dts/riscv/wch/ch32v208/ch32v208.dtsi

0 → 100644
+157 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <freq.h>

#include <mem.h>

#include <wch/qingke-v4c.dtsi>

#include <zephyr/dt-bindings/gpio/gpio.h>

#include <zephyr/dt-bindings/i2c/i2c.h>

#include <zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h>



/ {

	clocks {

		clk_hse: clk-hse {

			#clock-cells = <0>;

			compatible = "wch,ch32v00x-hse-clock";

			clock-frequency = <DT_FREQ_M(32)>;

			status = "disabled";

		};



		clk_hsi: clk-hsi {

			#clock-cells = <0>;

			compatible = "wch,ch32v00x-hsi-clock";

			clock-frequency = <DT_FREQ_M(8)>;

			status = "disabled";

		};



		clk_lsi: clk-lsi {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <DT_FREQ_K(32)>;

			status = "disabled";

		};



		pll: pll {

			#clock-cells = <0>;

			compatible = "wch,ch32v20x_30x-pll-clock";

			mul = <18>;

			status = "disabled";

		};

	};



	soc {

		sram0: memory@20000000 {

			compatible = "mmio-sram";

			reg = <0x20000000 DT_SIZE_K(64)>;

		};



		flash: flash-controller@40022000 {

			compatible = "wch,ch32v20x_30x-flash-controller";

			reg = <0x40022000 0x400>;

			#address-cells = <1>;

			#size-cells = <1>;



			flash0: flash@0 {

				compatible = "soc-nv-flash";

				reg = <0 DT_SIZE_K(128)>;

			};

		};



		pwr: pwr@40007000 {

			compatible = "wch,pwr";

			reg = <0x40007000 16>;

		};



		pinctrl: pin-controller@40010000 {

			compatible = "wch,20x_30x-afio";

			reg = <0x40010000 16>;

			#address-cells = <1>;

			#size-cells = <1>;



			gpioa: gpio@40010800 {

				compatible = "wch,gpio";

				reg = <0x40010800 0x20>;

				gpio-controller;

				#gpio-cells = <2>;

				ngpios = <8>;

				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>;

			};



			gpiob: gpio@40010C00 {

				compatible = "wch,gpio";

				reg = <0x40010C00 0x20>;

				gpio-controller;

				#gpio-cells = <2>;

				ngpios = <8>;

				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>;

			};



			gpioc: gpio@40011000 {

				compatible = "wch,gpio";

				reg = <0x40011000 0x20>;

				gpio-controller;

				#gpio-cells = <2>;

				ngpios = <8>;

				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>;

			};



			gpiod: gpio@40011400 {

				compatible = "wch,gpio";

				reg = <0x40011400 0x20>;

				gpio-controller;

				#gpio-cells = <2>;

				ngpios = <8>;

				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>;

			};

		};



		usart1: uart@40013800 {

			compatible = "wch,usart";

			reg = <0x40013800 0x20>;

			clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>;

			interrupt-parent = <&pfic>;

			interrupts = <53>;

			status = "disabled";

		};



		usart2: uart@40004400 {

			compatible = "wch,usart";

			reg = <0x40004400 0x20>;

			clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>;

			interrupt-parent = <&pfic>;

			interrupts = <54>;

			status = "disabled";

		};



		usart3: uart@40004800 {

			compatible = "wch,usart";

			reg = <0x40004800 0x20>;

			clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>;

			interrupt-parent = <&pfic>;

			interrupts = <55>;

			status = "disabled";

		};



		usart4: uart@40004c00 {

			compatible = "wch,usart";

			reg = <0x40004C00 0x20>;

			clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>;

			interrupt-parent = <&pfic>;

			interrupts = <68>;

			status = "disabled";

		};



		rcc: rcc@40021000 {

			compatible = "wch,rcc";

			reg = <0x40021000 16>;

			#clock-cells = <1>;

		};

	};

};



&cpu0 {

	clock-frequency = <DT_FREQ_M(144)>;

};

dts/riscv/wch/ch32v208/ch32v208cbu.dtsi

0 → 100644
+15 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <wch/ch32v208/ch32v208.dtsi>



&gpioc {

	gpio-reserved-ranges = <0 13>;

};



&gpiod {

	gpio-reserved-ranges = <0 16>;

};

dts/riscv/wch/ch32v208/ch32v208gbu.dtsi

0 → 100644
+23 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <wch/ch32v208/ch32v208.dtsi>



&gpioa {

	gpio-reserved-ranges = <8 3>, <15 1>;

};



&gpiob {

	gpio-reserved-ranges = <0 6>, <9 7>;

};



&gpioc {

	gpio-reserved-ranges = <0 7>, <10 4>;

};



&gpiod {

	gpio-reserved-ranges = <0 16>;

};

dts/riscv/wch/ch32v208/ch32v208rbt.dtsi

0 → 100644
+11 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <wch/ch32v208/ch32v208.dtsi>



&gpiod {

	gpio-reserved-ranges = <0 2>, <3 12>;

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE