drivers: stepper: tmc5xxx: generalized macros for tmc5xxx

/** Common Registers for TMC5041 and TMC51XX */

#if defined(CONFIG_STEPPER_ADI_TMC5041)

#define TMC5XXX_WRITE_BIT        0x80U

#define TMC5XXX_ADDRESS_MASK     0x7FU

 #define TMC5XXX_CLOCK_FREQ_SHIFT 24

#define TMC5XXX_GCONF 0x00

#define TMC5XXX_GSTAT 0x01

#define TMC5XXX_RAMPMODE_POSITIONING_MODE       0

#define TMC5XXX_RAMPMODE_POSITIVE_VELOCITY_MODE 1

#define TMC5XXX_RAMPMODE_NEGATIVE_VELOCITY_MODE 2

#define TMC5XXX_RAMPMODE_HOLD_MODE              3

#define TMC5XXX_SG_MIN_VALUE -64

#define TMC5XXX_SG_MAX_VALUE 63

#define TMC5XXX_SW_MODE_SG_STOP_ENABLE BIT(10)

#define TMC5XXX_COOLCONF_SG2_THRESHOLD_VALUE_SHIFT 16

#define TMC5XXX_IHOLD_MASK  GENMASK(4, 0)

#define TMC5XXX_IHOLD_SHIFT 0

#define TMC5XXX_IHOLD(n)    (((n) << TMC5XXX_IHOLD_SHIFT) & TMC5XXX_IHOLD_MASK)

#define TMC5XXX_IRUN_MASK  GENMASK(12, 8)

#define TMC5XXX_IRUN_SHIFT 8

#define TMC5XXX_IRUN(n)    (((n) << TMC5XXX_IRUN_SHIFT) & TMC5XXX_IRUN_MASK)

#define TMC5XXX_IHOLDDELAY_MASK  GENMASK(19, 16)

#define TMC5XXX_IHOLDDELAY_SHIFT 16

#define TMC5XXX_IHOLDDELAY(n)    (((n) << TMC5XXX_IHOLDDELAY_SHIFT) & TMC5XXX_IHOLDDELAY_MASK)

#define TMC5XXX_CHOPCONF_DRV_ENABLE_MASK GENMASK(3, 0)

#define TMC5XXX_CHOPCONF_MRES_MASK       GENMASK(27, 24)

#define TMC5XXX_CHOPCONF_MRES_SHIFT      24

#define TMC5XXX_RAMPSTAT_INT_MASK  GENMASK(7, 4)

#define TMC5XXX_RAMPSTAT_INT_SHIFT 4

#define TMC5XXX_RAMPSTAT_POS_REACHED_EVENT_MASK BIT(7)

#define TMC5XXX_POS_REACHED_EVENT                                                                  \

	(TMC5XXX_RAMPSTAT_POS_REACHED_EVENT_MASK >> TMC5XXX_RAMPSTAT_INT_SHIFT)

#define TMC5XXX_RAMPSTAT_STOP_SG_EVENT_MASK BIT(6)

#define TMC5XXX_STOP_SG_EVENT                                                                      \

	(TMC5XXX_RAMPSTAT_STOP_SG_EVENT_MASK >> TMC5XXX_RAMPSTAT_INT_SHIFT)

#define TMC5XXX_RAMPSTAT_STOP_RIGHT_EVENT_MASK BIT(5)

#define TMC5XXX_STOP_RIGHT_EVENT                                                                   \

	(TMC5XXX_RAMPSTAT_STOP_RIGHT_EVENT_MASK >> TMC5XXX_RAMPSTAT_INT_SHIFT)

#define TMC5XXX_RAMPSTAT_STOP_LEFT_EVENT_MASK BIT(4)

#define TMC5XXX_STOP_LEFT_EVENT                                                                    \

	(TMC5XXX_RAMPSTAT_STOP_LEFT_EVENT_MASK >> TMC5XXX_RAMPSTAT_INT_SHIFT)

#define TMC5XXX_DRV_STATUS_STST_BIT        BIT(31)

#define TMC5XXX_DRV_STATUS_SG_RESULT_MASK  GENMASK(9, 0)

#define TMC5XXX_DRV_STATUS_SG_STATUS_MASK  BIT(24)

#define TMC5XXX_DRV_STATUS_SG_STATUS_SHIFT 24

#endif

#ifdef CONFIG_STEPPER_ADI_TMC5041

 * @{

 */

#define TMC5041_WRITE_BIT    0x80U

#define TMC5041_ADDRESS_MASK 0x7FU

#define TMC5041_GCONF_POSCMP_ENABLE_SHIFT 3

#define TMC5041_GCONF_TEST_MODE_SHIFT     7

#define TMC5041_GCONF_SHAFT_SHIFT(n)      ((n) ? 8 : 9)

#define TMC5041_LOCK_GCONF_SHIFT          10

#define TMC5041_GCONF     0x00

#define TMC5041_GSTAT     0x01

#define TMC5041_INPUT     0x04

#define TMC5041_X_COMPARE 0x05

#define TMC5041_PWMCONF(motor)    (0x10 | TMC5041_MOTOR_ADDR_PWM(motor))

#define TMC5041_PWM_STATUS(motor) (0x11 | TMC5041_MOTOR_ADDR_PWM(motor))

#define TMC5041_COOLCONF(motor)   (0x6D | TMC5041_MOTOR_ADDR_DRV(motor))

#define TMC5041_DRVSTATUS(motor)  (0x6F | TMC5041_MOTOR_ADDR_DRV(motor))

#define TMC5041_RAMPMODE_POSITIONING_MODE       0

#define TMC5041_RAMPMODE_POSITIVE_VELOCITY_MODE 1

#define TMC5041_RAMPMODE_NEGATIVE_VELOCITY_MODE 2

#define TMC5041_RAMPMODE_HOLD_MODE              3

#define TMC5041_SW_MODE_SG_STOP_ENABLE BIT(10)

#define TMC5041_RAMPSTAT_INT_MASK  GENMASK(7, 4)

#define TMC5041_RAMPSTAT_INT_SHIFT 4

#define TMC5041_RAMPSTAT_POS_REACHED_EVENT_MASK BIT(7)

#define TMC5041_POS_REACHED_EVENT                                                                  \

	(TMC5041_RAMPSTAT_POS_REACHED_EVENT_MASK >> TMC5041_RAMPSTAT_INT_SHIFT)

#define TMC5041_RAMPSTAT_STOP_SG_EVENT_MASK BIT(6)

#define TMC5041_STOP_SG_EVENT	(TMC5041_RAMPSTAT_STOP_SG_EVENT_MASK >> TMC5041_RAMPSTAT_INT_SHIFT)

#define TMC5041_RAMPSTAT_STOP_RIGHT_EVENT_MASK BIT(5)

#define TMC5041_STOP_RIGHT_EVENT                                                                   \

	(TMC5041_RAMPSTAT_STOP_RIGHT_EVENT_MASK >> TMC5041_RAMPSTAT_INT_SHIFT)

#define TMC5041_RAMPSTAT_STOP_LEFT_EVENT_MASK BIT(4)

#define TMC5041_STOP_LEFT_EVENT                                                                    \

	(TMC5041_RAMPSTAT_STOP_LEFT_EVENT_MASK >> TMC5041_RAMPSTAT_INT_SHIFT)

#define TMC5041_DRV_STATUS_STST_BIT        BIT(31)

#define TMC5041_DRV_STATUS_SG_RESULT_MASK  GENMASK(9, 0)

#define TMC5041_DRV_STATUS_SG_STATUS_MASK  BIT(24)

#define TMC5041_DRV_STATUS_SG_STATUS_SHIFT 24

#define TMC5041_SG_MIN_VALUE -64

#define TMC5041_SG_MAX_VALUE 63

#define TMC5041_COOLCONF_SG2_THRESHOLD_VALUE_SHIFT 16

#define TMC5041_IHOLD_MASK  GENMASK(4, 0)

#define TMC5041_IHOLD_SHIFT 0

#define TMC5041_IHOLD(n)    (((n) << TMC5041_IHOLD_SHIFT) & TMC5041_IHOLD_MASK)

#define TMC5041_IRUN_MASK  GENMASK(12, 8)

#define TMC5041_IRUN_SHIFT 8

#define TMC5041_IRUN(n)    (((n) << TMC5041_IRUN_SHIFT) & TMC5041_IRUN_MASK)

#define TMC5041_IHOLDDELAY_MASK  GENMASK(19, 16)

#define TMC5041_IHOLDDELAY_SHIFT 16

#define TMC5041_IHOLDDELAY(n)    (((n) << TMC5041_IHOLDDELAY_SHIFT) & TMC5041_IHOLDDELAY_MASK)

#define TMC5041_CHOPCONF_DRV_ENABLE_MASK GENMASK(3, 0)

#define TMC5041_CHOPCONF_MRES_MASK       GENMASK(27, 24)

#define TMC5041_CHOPCONF_MRES_SHIFT      24

#endif

/**