soc: arm64: Add MMU table for Intel SoC FPGA Agilex

# Copyright (c) 2021 Intel Corporation

# SPDX-License-Identifier: Apache-2.0

zephyr_include_directories(.)

zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)

# Copyright (c) 2021 Intel Corporation

# SPDX-License-Identifier: Apache-2.0

if SOC_AGILEX

config SOC

	default "intel_socfpga_agilex"

# must be >= the highest interrupt number used

# - include the UART interrupts 173 or 204

config NUM_IRQS

	int

	default 205

config SYS_CLOCK_HW_CYCLES_PER_SEC

	int

	default 25000000

config KERNEL_VM_SIZE

	default 0x40000

endif

# Copyright (c) 2021 Intel Corporation

# SPDX-License-Identifier: Apache-2.0

if SOC_SERIES_AGILEX

config SOC_SERIES

	default "agilex"

source "soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex*"

endif # SOC_SERIES_AGILEX

# Copyright (c) 2021 Intel Corporation

# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_AGILEX

	bool "Intel SoC FPGA Agilex Series"

	select ARM64

	select CPU_CORTEX_A53

	select GIC_V2

	select SOC_FAMILY_INTEL_SOCFPGA

	help

		Enable support for Intel SoC FPGA Series

# Copyright (c) 2021 Intel Corporation

# SPDX-License-Identifier: Apache-2.0

choice

prompt "Intel SoC FPGA Agilex"

depends on SOC_SERIES_AGILEX

config SOC_AGILEX

	bool "Intel SoC FPGA Agilex"

endchoice