Commit e6dd68ec authored by Yong Cong Sin's avatar Yong Cong Sin Committed by Benjamin Cabé
Browse files

arch: riscv: introduce `CONFIG_RISCV_GP_PURPOSE` choice 



Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only
one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be
enabled, instead of relying of dependencies.

To do that, introduce a new
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected
by SoC when it implemented global pointer (GP) initialization for
relative addressing in its linker.

`CONFIG_RISCV_GP` will be the default choice when
`CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y`

Signed-off-by: default avatarYong Cong Sin <ycsin@meta.com>
Signed-off-by: default avatarYong Cong Sin <yongcong.sin@gmail.com>
parent 033804e2

arch/riscv/Kconfig

+13 −2
Original line number Diff line number Diff line
@@ -16,9 +16,13 @@ config FLOAT_HARD 
	help

	  This option enables the hard-float calling convention.



choice RISCV_GP_PURPOSE

	prompt "Purpose of the global pointer (GP) register"

	default RISCV_GP if RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING



config RISCV_GP

	bool "RISC-V global pointer relative addressing"

	default n

	depends on RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING

	help

	  Use global pointer relative addressing for small globals declared

	  anywhere in the executable. It can benefit performance and reduce
@@ -30,7 +34,6 @@ config RISCV_GP 


config RISCV_CURRENT_VIA_GP

	bool "Store current thread into the global pointer (GP) register"

	depends on !RISCV_GP

	depends on MP_MAX_NUM_CPUS > 1

	select ARCH_HAS_CUSTOM_CURRENT_IMPL

	help
@@ -38,6 +41,8 @@ config RISCV_CURRENT_VIA_GP 
	  When is enabled, calls to `arch_current_thread()` & `k_sched_current_thread_query()` will

	  be reduced to a single register read.



endchoice # RISCV_GP_PURPOSE



config RISCV_ALWAYS_SWITCH_THROUGH_ECALL

	bool "Do not use mret outside a trap handler context"

	depends on MULTITHREADING
@@ -148,6 +153,12 @@ config RISCV_SOC_HAS_CUSTOM_SYS_IO 
	  the RISC-V SoC needs to do something different and more than reading and

	  writing the registers.



config RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING

	bool

	help

	  Selected when SoC has implemented the initialization of global pointer (GP)

	  at program start, or earlier than any instruction using GP relative addressing.



config RISCV_SOC_CONTEXT_SAVE

	bool "SOC-based context saving in IRQ handlers"

	select RISCV_SOC_OFFSETS

soc/andestech/ae350/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ config SOC_SERIES_ANDES_AE350 
	select RISCV

	select RISCV_PRIVILEGED

	select RISCV_HAS_PLIC

	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING

	imply XIP



config SOC_ANDES_AE350

soc/andestech/ae350/Kconfig.defconfig

+0 −3
Original line number Diff line number Diff line
@@ -21,9 +21,6 @@ config RISCV_GENERIC_TOOLCHAIN 
config RISCV_SOC_INTERRUPT_INIT

	default y



config RISCV_GP

	default y



config 2ND_LVL_ISR_TBL_OFFSET

	default 12

soc/espressif/esp32c2/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 


config SOC_SERIES_ESP32C2

	select RISCV

	select RISCV_GP

	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING

	select DYNAMIC_INTERRUPTS

	select CLOCK_CONTROL

	select PINCTRL

soc/espressif/esp32c3/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 


config SOC_SERIES_ESP32C3

	select RISCV

	select RISCV_GP

	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING

	select DYNAMIC_INTERRUPTS

	select CLOCK_CONTROL

	select PINCTRL

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