drivers: mspi_dw: Improve transfer handling

- use separate code paths for TX and RX in ISR
- make sending of dummy bytes in the single line mode (Standard
  SPI) more consistent so it can be easily extended
- use value 0 instead of 0xAA for dummy bytes as there is normally
  no point in making noise one the MOSI line when only receiving
  data (it can only be useful in debugging transfers)
- move all writing of data in the TX FIFO to ISR to avoid broken
  transfers in the single line mode (where the clock stretching
  is not available) when the driver is preempted right before it
  enables interrupts
- use the TX FIFO start level also for transfers without data,
  so that it's not possible that the TX FIFO gets emptied between
  the writes of command and address fields in the single line mode
- add a few comments to explain better how transfers are handled

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>