Commit e4341a40 authored by Lucien Zhao's avatar Lucien Zhao Committed by Carles Cufi
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soc: nxp: imxrt: imxrt118x: Enable GPT1/2 clock



dts: arm: nxp: mimxrt1180_evk: add GPT1/2 instance into devicetree

Enable GPT1/2 clock
Add GPT1/GPT2 instances
Set GPT2 as a counter, the default frequency is 240000000

Signed-off-by: default avatarLucien Zhao <lucien.zhao@nxp.com>
parent 5ce7845f
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+17 −0
Original line number Diff line number Diff line
@@ -276,6 +276,23 @@
		clocks = <&ccm IMX_CCM_LPI2C0506_CLK 0x80 24>;
		status = "disabled";
	};

	gpt1: gpt@46c0000 {
		compatible = "nxp,imx-gpt";
		reg = <0x46c0000 0x4000>;
		interrupts = <209 0>;
		gptfreq = <240000000>;
		clocks = <&ccm IMX_CCM_GPT1_CLK 0x41 0>;
		status = "disabled";
	};

	gpt2: gpt@2ec0000 {
		compatible = "nxp,imx-gpt";
		reg = <0x2ec0000 0x4000>;
		interrupts = <210 0>;
		gptfreq = <240000000>;
		clocks = <&ccm IMX_CCM_GPT2_CLK 0x41 0>;
	};
};

&flexspi1 {
+18 −0
Original line number Diff line number Diff line
@@ -251,6 +251,24 @@ static ALWAYS_INLINE void clock_init(void)
	CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg);
#endif

#if defined(CONFIG_COUNTER_MCUX_GPT)

#if (DT_NODE_HAS_STATUS(DT_NODELABEL(gpt1), okay))
	/* Configure GPT1 using SYS_PLL3_DIV2_CLK */
	rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2;
	rootCfg.div = 1;
	CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpt1), okay) */

#if (DT_NODE_HAS_STATUS(DT_NODELABEL(gpt2), okay))
	/* Configure GPT2 using SYS_PLL3_DIV2_CLK */
	rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2;
	rootCfg.div = 1;
	CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpt2), okay) */

#endif /* CONFIG_COUNTER_MCUX_GPT */

	/* Keep core clock ungated during WFI */
	CCM->LPCG[1].LPM0 = 0x33333333;
	CCM->LPCG[1].LPM1 = 0x33333333;