Commit e382969f authored by Hubert Guan's avatar Hubert Guan Committed by Carles Cufi
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include: zephyr: dt-bindings: clock: Rename domain clock selection macro 



Rename from STM32_CLOCK to STM32_DOMAIN_CLOCK since it conflicts with
new macro name.

Signed-off-by: default avatarHubert Guan <hguan@ucsb.edu>
parent d2273c02

include/zephyr/dt-bindings/clock/stm32c0_clock.h

+6 −6
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ 
 * @param mask Mask for the RCC_CCIPRx field.

 * @param val Clock value (0, 1, ... 7).

 */

#define STM32_CLOCK(val, mask, shift, reg)					\

#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\

	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\

	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\

	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
@@ -68,12 +68,12 @@ 


/** @brief Device domain clocks selection helpers */

/** CCIPR devices */

#define USART1_SEL(val)		STM32_CLOCK(val, 3, 0, CCIPR_REG)

#define I2C1_SEL(val)		STM32_CLOCK(val, 3, 12, CCIPR_REG)

#define I2C2_I2S1_SEL(val)	STM32_CLOCK(val, 3, 14, CCIPR_REG)

#define ADC_SEL(val)		STM32_CLOCK(val, 3, 30, CCIPR_REG)

#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)

#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)

#define I2C2_I2S1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)

#define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)

/** CSR1 devices */

#define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, CSR1_REG)

#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, CSR1_REG)



/** CFGR1 devices */

#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG)

include/zephyr/dt-bindings/clock/stm32f0_clock.h

+8 −8
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ 
 * @param mask Mask for the RCC_CFGRx field.

 * @param val Clock value (0, 1, ... 7).

 */

#define STM32_CLOCK(val, mask, shift, reg)					\

#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\

	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\

	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\

	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
@@ -67,14 +67,14 @@ 


/** @brief Device domain clocks selection helpers */

/** CFGR3 devices */

#define USART1_SEL(val)		STM32_CLOCK(val, 3, 0, CFGR3_REG)

#define I2C1_SEL(val)		STM32_CLOCK(val, 1, 4, CFGR3_REG)

#define CEC_SEL(val)		STM32_CLOCK(val, 1, 6, CFGR3_REG)

#define USB_SEL(val)		STM32_CLOCK(val, 1, 7, CFGR3_REG)

#define USART2_SEL(val)		STM32_CLOCK(val, 3, 16, CFGR3_REG)

#define USART3_SEL(val)		STM32_CLOCK(val, 3, 18, CFGR3_REG)

#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)

#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)

#define CEC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)

#define USB_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 7, CFGR3_REG)

#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)

#define USART3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)

/** BDCR devices */

#define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, BDCR_REG)

#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)



/** CFGR1 devices */

#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)

include/zephyr/dt-bindings/clock/stm32f1_clock.h

+4 −4
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ 
 * @param mask Mask for the RCC_CFGRx field.

 * @param val Clock value (0, 1, ... 7).

 */

#define STM32_CLOCK(val, mask, shift, reg)					\

#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\

	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\

	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\

	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
@@ -64,10 +64,10 @@ 


/** @brief Device domain clocks selection helpers */

/** CFGR2 devices */

#define I2S2_SEL(val)		STM32_CLOCK(val, 1, 17, CFGR2_REG)

#define I2S3_SEL(val)		STM32_CLOCK(val, 1, 18, CFGR2_REG)

#define I2S2_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 17, CFGR2_REG)

#define I2S3_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 18, CFGR2_REG)

/** BDCR devices */

#define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, BDCR_REG)

#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)



/** CFGR1 devices */

#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG)

include/zephyr/dt-bindings/clock/stm32f3_clock.h

+19 −19
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ 
 * @param mask Mask for the RCC_CFGRx field.

 * @param val Clock value (0, 1, ... 7).

 */

#define STM32_CLOCK(val, mask, shift, reg)					\

#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\

	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\

	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\

	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
@@ -68,27 +68,27 @@ 


/** @brief Device domain clocks selection helpers) */

/** CFGR devices */

#define I2S_SEL(val)		STM32_CLOCK(val, 1, 23, CFGR_REG)

#define I2S_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)

#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)

#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG)

/** CFGR3 devices */

#define USART1_SEL(val)		STM32_CLOCK(val, 3, 0, CFGR3_REG)

#define I2C1_SEL(val)		STM32_CLOCK(val, 1, 4, CFGR3_REG)

#define I2C2_SEL(val)		STM32_CLOCK(val, 1, 5, CFGR3_REG)

#define I2C3_SEL(val)		STM32_CLOCK(val, 1, 6, CFGR3_REG)

#define TIM1_SEL(val)		STM32_CLOCK(val, 1, 8, CFGR3_REG)

#define TIM8_SEL(val)		STM32_CLOCK(val, 1, 9, CFGR3_REG)

#define TIM15_SEL(val)		STM32_CLOCK(val, 1, 10, CFGR3_REG)

#define TIM16_SEL(val)		STM32_CLOCK(val, 1, 11, CFGR3_REG)

#define TIM17_SEL(val)		STM32_CLOCK(val, 1, 13, CFGR3_REG)

#define TIM20_SEL(val)		STM32_CLOCK(val, 1, 15, CFGR3_REG)

#define USART2_SEL(val)		STM32_CLOCK(val, 3, 16, CFGR3_REG)

#define USART3_SEL(val)		STM32_CLOCK(val, 3, 18, CFGR3_REG)

#define USART4_SEL(val)		STM32_CLOCK(val, 3, 20, CFGR3_REG)

#define USART5_SEL(val)		STM32_CLOCK(val, 3, 22, CFGR3_REG)

#define TIM2_SEL(val)		STM32_CLOCK(val, 1, 24, CFGR3_REG)

#define TIM3_4_SEL(val)		STM32_CLOCK(val, 1, 25, CFGR3_REG)

#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)

#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)

#define I2C2_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG)

#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)

#define TIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG)

#define TIM8_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 9, CFGR3_REG)

#define TIM15_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 10, CFGR3_REG)

#define TIM16_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 11, CFGR3_REG)

#define TIM17_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 13, CFGR3_REG)

#define TIM20_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 15, CFGR3_REG)

#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)

#define USART3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)

#define USART4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CFGR3_REG)

#define USART5_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, CFGR3_REG)

#define TIM2_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 24, CFGR3_REG)

#define TIM3_4_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 25, CFGR3_REG)

/** BDCR devices */

#define RTC_SEL(val)		STM32_CLOCK(val, 3, 8, BDCR_REG)

#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)



#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32f410_clock.h

+11 −11
Original line number Diff line number Diff line
@@ -12,19 +12,19 @@ 


/** @brief Device domain clocks selection helpers */

/** DCKCFGR devices */

#define CKDFSDM2A_SEL(val)	STM32_CLOCK(val, 1, 14, DCKCFGR_REG)

#define CKDFSDM1A_SEL(val)	STM32_CLOCK(val, 1, 15, DCKCFGR_REG)

#define SAI1A_SEL(val)		STM32_CLOCK(val, 3, 20, DCKCFGR_REG)

#define SAI1B_SEL(val)		STM32_CLOCK(val, 3, 22, DCKCFGR_REG)

#define I2S1_SEL(val)		STM32_CLOCK(val, 3, 25, DCKCFGR_REG)

#define I2S2_SEL(val)		STM32_CLOCK(val, 3, 27, DCKCFGR_REG)

#define CKDFSDM_SEL(val)	STM32_CLOCK(val, 1, 31, DCKCFGR_REG)

#define CKDFSDM2A_SEL(val)	STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG)

#define CKDFSDM1A_SEL(val)	STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG)

#define SAI1A_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG)

#define SAI1B_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG)

#define I2S1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 25, DCKCFGR_REG)

#define I2S2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 27, DCKCFGR_REG)

#define CKDFSDM_SEL(val)	STM32_DOMAIN_CLOCK(val, 1, 31, DCKCFGR_REG)



/** DCKCFGR2 devices */

#define I2CFMP1_SEL(val)	STM32_CLOCK(val, 3, 22, DCKCFGR2_REG)

#define CK48M_SEL(val)		STM32_CLOCK(val, 1, 27, DCKCFGR2_REG)

#define SDIO_SEL(val)		STM32_CLOCK(val, 1, 28, DCKCFGR2_REG)

#define LPTIM1_SEL(val)		STM32_CLOCK(val, 3, 30, DCKCFGR2_REG)

#define I2CFMP1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)

#define CK48M_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)

#define SDIO_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)

#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 30, DCKCFGR2_REG)



/* F4 generic I2S_SEL is not compatible with F410 devices */

#ifdef I2S_SEL

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