soc: nxp: imxrt118x: update MPU configuration

#include <zephyr/devicetree.h>

#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>

#define REGION_HYPERRAM_BASE_ADDRESS   0x04000000

#define REGION_HYPERRAM_SIZE           0x04000000

#define REGION_DTCM_BASE_ADDRESS       0x20000000

#define REGION_FLEXSPI2_BASE_ADDRESS   0x14000000

#define REGION_FLEXSPI2_SIZE           0x04000000

#define REGION_DTCM_BASE_ADDRESS       0x30000000

#define REGION_DTCM_SIZE               0x00020000

#define REGION_FLEXSPI_BASE_ADDRESS    0x28000000

#define REGION_FLEXSPI_BASE_ADDRESS    0x38000000

#define REGION_FLEXSPI_SIZE            0x08000000

#define REGION_PERIPHERAL_BASE_ADDRESS 0x40000000

#define REGION_PERIPHERAL_BASE_ADDRESS 0x50000000

#define REGION_PERIPHERAL_SIZE         0x40000000

static const struct arm_mpu_region mpu_regions[] = {

	MPU_REGION_ENTRY("HYPERRAM", REGION_HYPERRAM_BASE_ADDRESS,

			 REGION_RAM_ATTR(REGION_HYPERRAM_BASE_ADDRESS, REGION_HYPERRAM_SIZE)),

	MPU_REGION_ENTRY("FLEXSPI2", REGION_FLEXSPI2_BASE_ADDRESS,

			 REGION_RAM_ATTR(REGION_FLEXSPI2_BASE_ADDRESS, REGION_FLEXSPI2_SIZE)),

	MPU_REGION_ENTRY("FLEXSPI", REGION_FLEXSPI_BASE_ADDRESS,

			 REGION_FLASH_ATTR(REGION_FLEXSPI_BASE_ADDRESS, REGION_FLEXSPI_SIZE)),

	MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS,