Commit e08a77c8 authored by Filip Kokosinski's avatar Filip Kokosinski Committed by Carles Cufi
Browse files

dts/riscv/efinix: add the `efinix,vexriscv-sapphire` compatible string 



This commit adds the `efinix,vexriscv-sapphire` compatible string. This
helps identify the core type from the final devicetree alone.

The VexRiscv core configuration is specific to the Efinix Sapphire SoC.

Signed-off-by: default avatarFilip Kokosinski <fkokosinski@antmicro.com>
parent 0458ac06

dts/bindings/cpu/efinix,vexriscv-sapphire.yaml

0 → 100644
+9 −0
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# Copyright (c) 2024 Antmicro <www.antmicro.com>

#

# SPDX-License-Identifier: Apache-2.0



description: VexRiscv core with the configuration as used in the Efinix Sapphire SoC



compatible: "efinix,vexriscv-sapphire"



include: riscv,cpus.yaml

dts/riscv/efinix/sapphire_soc.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ 
		#size-cells = <0>;

		cpu@0 {

			clock-frequency = <100000000>;

			compatible = "riscv";

			compatible = "efinix,vexriscv-sapphire", "riscv";

			device_type = "cpu";

			reg = <0>;

			riscv,isa = "rv32ima_zicsr_zifencei";

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