driver: bbram: npcx: update bbram status register bit offset for npck3 (dbc49f04) · Commits · Wenxi XU / zephyr

drivers/bbram/Kconfig.npcx

+8 −0

Original line number	Diff line number	Diff line
		@@ -24,3 +24,11 @@ config BBRAM_NPCX_STATUS_REG_WRITE_WORKAROUND
		A write operation to the BKUP_STS register might disable write to all
		the Battery-Backed RAM. The workaround is to read the BKUP_STS
		register after every write to this register.

		config BBRAM_NPCX_EX
		bool "Extended NPCX BBRAM driver support"
		default y
		depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NUVOTON_NPCX_BBRAM),support-npckn-v1,True)
		help
		This option enables extended BBRAM support for NPCKn variant of
		processors.

drivers/bbram/bbram_npcx.c

+19 −8

Original line number	Diff line number	Diff line
		@@ -15,9 +15,16 @@ LOG_MODULE_REGISTER(npcx_bbram, CONFIG_BBRAM_LOG_LEVEL);

		#include "npcx.h"

		#define NPCX_STATUS_IBBR BIT(7)
		#define NPCX_STATUS_VSBY BIT(1)
		#define NPCX_STATUS_VCC1 BIT(0)
		/*
		* For emulator, define status bits for backup RAM status register.
		* These are required for the emulator (native_sim) since the npcx SOC
		* is not enabled, and missing definitions would cause a build error.
		*/
		#ifdef CONFIG_BBRAM_NPCX_EMUL
		#define NPCX_BKUPSTS_VSBY_STS BIT(1)
		#define NPCX_BKUPSTS_VCC1_STS BIT(0)
		#define NPCX_BKUPSTS_IBBR BIT(7)
		#endif

		#define DRV_STATUS(dev) \
		(((volatile uint8_t )((const struct bbram_npcx_config *)(dev)->config)->status_reg_addr))
		@@ -48,17 +55,19 @@ static int get_bit_and_reset(const struct device *dev, int mask)

		static int bbram_npcx_check_invalid(const struct device *dev)
		{
		return get_bit_and_reset(dev, NPCX_STATUS_IBBR);
		return get_bit_and_reset(dev, NPCX_BKUPSTS_IBBR);
		}

		#ifndef CONFIG_BBRAM_NPCX_EX
		static int bbram_npcx_check_standby_power(const struct device *dev)
		{
		return get_bit_and_reset(dev, NPCX_STATUS_VSBY);
		return get_bit_and_reset(dev, NPCX_BKUPSTS_VSBY_STS);
		}
		#endif /* CONFIG_BBRAM_NPCX_EX */

		static int bbram_npcx_check_power(const struct device *dev)
		{
		return get_bit_and_reset(dev, NPCX_STATUS_VCC1);
		return get_bit_and_reset(dev, NPCX_BKUPSTS_VCC1_STS);
		}

		static int bbram_npcx_get_size(const struct device dev, size_t size)
		@@ -97,7 +106,9 @@ static int bbram_npcx_write(const struct device *dev, size_t offset, size_t size

		static DEVICE_API(bbram, bbram_npcx_driver_api) = {
		.check_invalid = bbram_npcx_check_invalid,
		#ifndef CONFIG_BBRAM_NPCX_EX
		.check_standby_power = bbram_npcx_check_standby_power,
		#endif /* CONFIG_BBRAM_NPCX_EX */
		.check_power = bbram_npcx_check_power,
		.get_size = bbram_npcx_get_size,
		.read = bbram_npcx_read,

dts/arm/nuvoton/npck/npck.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -74,6 +74,7 @@
		reg = <0x400af000 0x100
		0x400af100 0x1>;
		reg-names = "memory", "status";
		support-npckn-v1;
		};

		pcc: clock-controller@4000d000 {

dts/bindings/memory-controllers/nuvoton,npcx-bbram.yaml

+4 −0

Original line number	Diff line number	Diff line
		@@ -10,3 +10,7 @@ include: base.yaml
		properties:
		reg:
		required: true
		support-npckn-v1:
		type: boolean
		description: \|
		This option enables the bbram driver for NPCKn.

soc/nuvoton/npcx/common/npckn/include/reg_def.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -1955,4 +1955,8 @@ struct gdma_reg {
		#define NPCX_DMACTL_GDMAERR 20
		#define NPCX_DMACTL_BUSY_EN 23

		/* BBRM register fields */
		#define NPCX_BKUPSTS_VCC1_STS BIT(5)
		#define NPCX_BKUPSTS_IBBR BIT(7)

		#endif /* _NUVOTON_NPCX_REG_DEF_H */

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