Loading include/zephyr/net/mii.h +48 −46 Original line number Diff line number Diff line Loading @@ -12,6 +12,8 @@ #ifndef ZEPHYR_INCLUDE_NET_MII_H_ #define ZEPHYR_INCLUDE_NET_MII_H_ #include <zephyr/sys/util_macro.h> /** * @brief Ethernet MII (media independent interface) functions * @defgroup ethernet_mii Ethernet MII Support Functions Loading Loading @@ -53,86 +55,86 @@ /* Basic Mode Control Register (BMCR) bit definitions */ /** PHY reset */ #define MII_BMCR_RESET (1 << 15) #define MII_BMCR_RESET BIT(15) /** enable loopback mode */ #define MII_BMCR_LOOPBACK (1 << 14) #define MII_BMCR_LOOPBACK BIT(14) /** 10=1000Mbps 01=100Mbps; 00=10Mbps */ #define MII_BMCR_SPEED_LSB (1 << 13) #define MII_BMCR_SPEED_LSB BIT(13) /** Auto-Negotiation enable */ #define MII_BMCR_AUTONEG_ENABLE (1 << 12) #define MII_BMCR_AUTONEG_ENABLE BIT(12) /** power down mode */ #define MII_BMCR_POWER_DOWN (1 << 11) #define MII_BMCR_POWER_DOWN BIT(11) /** isolate electrically PHY from MII */ #define MII_BMCR_ISOLATE (1 << 10) #define MII_BMCR_ISOLATE BIT(10) /** restart auto-negotiation */ #define MII_BMCR_AUTONEG_RESTART (1 << 9) #define MII_BMCR_AUTONEG_RESTART BIT(9) /** full duplex mode */ #define MII_BMCR_DUPLEX_MODE (1 << 8) #define MII_BMCR_DUPLEX_MODE BIT(8) /** 10=1000Mbps 01=100Mbps; 00=10Mbps */ #define MII_BMCR_SPEED_MSB (1 << 6) #define MII_BMCR_SPEED_MSB BIT(6) /** Link Speed Field */ #define MII_BMCR_SPEED_MASK (1 << 6 | 1 << 13) #define MII_BMCR_SPEED_MASK (BIT(6) | BIT(13)) /** select speed 10 Mb/s */ #define MII_BMCR_SPEED_10 (0 << 6 | 0 << 13) #define MII_BMCR_SPEED_10 0 /** select speed 100 Mb/s */ #define MII_BMCR_SPEED_100 (0 << 6 | 1 << 13) #define MII_BMCR_SPEED_100 BIT(13) /** select speed 1000 Mb/s */ #define MII_BMCR_SPEED_1000 (1 << 6 | 0 << 13) #define MII_BMCR_SPEED_1000 BIT(6) /* Basic Mode Status Register (BMSR) bit definitions */ /** 100BASE-T4 capable */ #define MII_BMSR_100BASE_T4 (1 << 15) #define MII_BMSR_100BASE_T4 BIT(15) /** 100BASE-X full duplex capable */ #define MII_BMSR_100BASE_X_FULL (1 << 14) #define MII_BMSR_100BASE_X_FULL BIT(14) /** 100BASE-X half duplex capable */ #define MII_BMSR_100BASE_X_HALF (1 << 13) #define MII_BMSR_100BASE_X_HALF BIT(13) /** 10 Mb/s full duplex capable */ #define MII_BMSR_10_FULL (1 << 12) #define MII_BMSR_10_FULL BIT(12) /** 10 Mb/s half duplex capable */ #define MII_BMSR_10_HALF (1 << 11) #define MII_BMSR_10_HALF BIT(11) /** 100BASE-T2 full duplex capable */ #define MII_BMSR_100BASE_T2_FULL (1 << 10) #define MII_BMSR_100BASE_T2_FULL BIT(10) /** 100BASE-T2 half duplex capable */ #define MII_BMSR_100BASE_T2_HALF (1 << 9) #define MII_BMSR_100BASE_T2_HALF BIT(9) /** extend status information in reg 15 */ #define MII_BMSR_EXTEND_STATUS (1 << 8) #define MII_BMSR_EXTEND_STATUS BIT(8) /** PHY accepts management frames with preamble suppressed */ #define MII_BMSR_MF_PREAMB_SUPPR (1 << 6) #define MII_BMSR_MF_PREAMB_SUPPR BIT(6) /** Auto-negotiation process completed */ #define MII_BMSR_AUTONEG_COMPLETE (1 << 5) #define MII_BMSR_AUTONEG_COMPLETE BIT(5) /** remote fault detected */ #define MII_BMSR_REMOTE_FAULT (1 << 4) #define MII_BMSR_REMOTE_FAULT BIT(4) /** PHY is able to perform Auto-Negotiation */ #define MII_BMSR_AUTONEG_ABILITY (1 << 3) #define MII_BMSR_AUTONEG_ABILITY BIT(3) /** link is up */ #define MII_BMSR_LINK_STATUS (1 << 2) #define MII_BMSR_LINK_STATUS BIT(2) /** jabber condition detected */ #define MII_BMSR_JABBER_DETECT (1 << 1) #define MII_BMSR_JABBER_DETECT BIT(1) /** extended register capabilities */ #define MII_BMSR_EXTEND_CAPAB (1 << 0) #define MII_BMSR_EXTEND_CAPAB BIT(0) /* Auto-negotiation Advertisement Register (ANAR) bit definitions */ /* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */ /** next page */ #define MII_ADVERTISE_NEXT_PAGE (1 << 15) #define MII_ADVERTISE_NEXT_PAGE BIT(15) /** link partner acknowledge response */ #define MII_ADVERTISE_LPACK (1 << 14) #define MII_ADVERTISE_LPACK BIT(14) /** remote fault */ #define MII_ADVERTISE_REMOTE_FAULT (1 << 13) #define MII_ADVERTISE_REMOTE_FAULT BIT(13) /** try for asymmetric pause */ #define MII_ADVERTISE_ASYM_PAUSE (1 << 11) #define MII_ADVERTISE_ASYM_PAUSE BIT(11) /** try for pause */ #define MII_ADVERTISE_PAUSE (1 << 10) #define MII_ADVERTISE_PAUSE BIT(10) /** try for 100BASE-T4 support */ #define MII_ADVERTISE_100BASE_T4 (1 << 9) #define MII_ADVERTISE_100BASE_T4 BIT(9) /** try for 100BASE-X full duplex support */ #define MII_ADVERTISE_100_FULL (1 << 8) #define MII_ADVERTISE_100_FULL BIT(8) /** try for 100BASE-X support */ #define MII_ADVERTISE_100_HALF (1 << 7) #define MII_ADVERTISE_100_HALF BIT(7) /** try for 10 Mb/s full duplex support */ #define MII_ADVERTISE_10_FULL (1 << 6) #define MII_ADVERTISE_10_FULL BIT(6) /** try for 10 Mb/s half duplex support */ #define MII_ADVERTISE_10_HALF (1 << 5) #define MII_ADVERTISE_10_HALF BIT(5) /** Selector Field Mask */ #define MII_ADVERTISE_SEL_MASK (0x1F << 0) /** Selector Field */ Loading @@ -140,9 +142,9 @@ /* 1000BASE-T Control Register bit definitions */ /** try for 1000BASE-T full duplex support */ #define MII_ADVERTISE_1000_FULL (1 << 9) #define MII_ADVERTISE_1000_FULL BIT(9) /** try for 1000BASE-T half duplex support */ #define MII_ADVERTISE_1000_HALF (1 << 8) #define MII_ADVERTISE_1000_HALF BIT(8) /** Advertise all speeds */ #define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\ Loading @@ -151,13 +153,13 @@ /* Extended Status Register bit definitions */ /** 1000BASE-X full-duplex capable */ #define MII_ESTAT_1000BASE_X_FULL (1 << 15) #define MII_ESTAT_1000BASE_X_FULL BIT(15) /** 1000BASE-X half-duplex capable */ #define MII_ESTAT_1000BASE_X_HALF (1 << 14) #define MII_ESTAT_1000BASE_X_HALF BIT(14) /** 1000BASE-T full-duplex capable */ #define MII_ESTAT_1000BASE_T_FULL (1 << 13) #define MII_ESTAT_1000BASE_T_FULL BIT(13) /** 1000BASE-T half-duplex capable */ #define MII_ESTAT_1000BASE_T_HALF (1 << 12) #define MII_ESTAT_1000BASE_T_HALF BIT(12) /* MMD Access Control Register (MII_MMD_ACR) Register bit definitions */ /** DEVAD Mask */ Loading Loading
include/zephyr/net/mii.h +48 −46 Original line number Diff line number Diff line Loading @@ -12,6 +12,8 @@ #ifndef ZEPHYR_INCLUDE_NET_MII_H_ #define ZEPHYR_INCLUDE_NET_MII_H_ #include <zephyr/sys/util_macro.h> /** * @brief Ethernet MII (media independent interface) functions * @defgroup ethernet_mii Ethernet MII Support Functions Loading Loading @@ -53,86 +55,86 @@ /* Basic Mode Control Register (BMCR) bit definitions */ /** PHY reset */ #define MII_BMCR_RESET (1 << 15) #define MII_BMCR_RESET BIT(15) /** enable loopback mode */ #define MII_BMCR_LOOPBACK (1 << 14) #define MII_BMCR_LOOPBACK BIT(14) /** 10=1000Mbps 01=100Mbps; 00=10Mbps */ #define MII_BMCR_SPEED_LSB (1 << 13) #define MII_BMCR_SPEED_LSB BIT(13) /** Auto-Negotiation enable */ #define MII_BMCR_AUTONEG_ENABLE (1 << 12) #define MII_BMCR_AUTONEG_ENABLE BIT(12) /** power down mode */ #define MII_BMCR_POWER_DOWN (1 << 11) #define MII_BMCR_POWER_DOWN BIT(11) /** isolate electrically PHY from MII */ #define MII_BMCR_ISOLATE (1 << 10) #define MII_BMCR_ISOLATE BIT(10) /** restart auto-negotiation */ #define MII_BMCR_AUTONEG_RESTART (1 << 9) #define MII_BMCR_AUTONEG_RESTART BIT(9) /** full duplex mode */ #define MII_BMCR_DUPLEX_MODE (1 << 8) #define MII_BMCR_DUPLEX_MODE BIT(8) /** 10=1000Mbps 01=100Mbps; 00=10Mbps */ #define MII_BMCR_SPEED_MSB (1 << 6) #define MII_BMCR_SPEED_MSB BIT(6) /** Link Speed Field */ #define MII_BMCR_SPEED_MASK (1 << 6 | 1 << 13) #define MII_BMCR_SPEED_MASK (BIT(6) | BIT(13)) /** select speed 10 Mb/s */ #define MII_BMCR_SPEED_10 (0 << 6 | 0 << 13) #define MII_BMCR_SPEED_10 0 /** select speed 100 Mb/s */ #define MII_BMCR_SPEED_100 (0 << 6 | 1 << 13) #define MII_BMCR_SPEED_100 BIT(13) /** select speed 1000 Mb/s */ #define MII_BMCR_SPEED_1000 (1 << 6 | 0 << 13) #define MII_BMCR_SPEED_1000 BIT(6) /* Basic Mode Status Register (BMSR) bit definitions */ /** 100BASE-T4 capable */ #define MII_BMSR_100BASE_T4 (1 << 15) #define MII_BMSR_100BASE_T4 BIT(15) /** 100BASE-X full duplex capable */ #define MII_BMSR_100BASE_X_FULL (1 << 14) #define MII_BMSR_100BASE_X_FULL BIT(14) /** 100BASE-X half duplex capable */ #define MII_BMSR_100BASE_X_HALF (1 << 13) #define MII_BMSR_100BASE_X_HALF BIT(13) /** 10 Mb/s full duplex capable */ #define MII_BMSR_10_FULL (1 << 12) #define MII_BMSR_10_FULL BIT(12) /** 10 Mb/s half duplex capable */ #define MII_BMSR_10_HALF (1 << 11) #define MII_BMSR_10_HALF BIT(11) /** 100BASE-T2 full duplex capable */ #define MII_BMSR_100BASE_T2_FULL (1 << 10) #define MII_BMSR_100BASE_T2_FULL BIT(10) /** 100BASE-T2 half duplex capable */ #define MII_BMSR_100BASE_T2_HALF (1 << 9) #define MII_BMSR_100BASE_T2_HALF BIT(9) /** extend status information in reg 15 */ #define MII_BMSR_EXTEND_STATUS (1 << 8) #define MII_BMSR_EXTEND_STATUS BIT(8) /** PHY accepts management frames with preamble suppressed */ #define MII_BMSR_MF_PREAMB_SUPPR (1 << 6) #define MII_BMSR_MF_PREAMB_SUPPR BIT(6) /** Auto-negotiation process completed */ #define MII_BMSR_AUTONEG_COMPLETE (1 << 5) #define MII_BMSR_AUTONEG_COMPLETE BIT(5) /** remote fault detected */ #define MII_BMSR_REMOTE_FAULT (1 << 4) #define MII_BMSR_REMOTE_FAULT BIT(4) /** PHY is able to perform Auto-Negotiation */ #define MII_BMSR_AUTONEG_ABILITY (1 << 3) #define MII_BMSR_AUTONEG_ABILITY BIT(3) /** link is up */ #define MII_BMSR_LINK_STATUS (1 << 2) #define MII_BMSR_LINK_STATUS BIT(2) /** jabber condition detected */ #define MII_BMSR_JABBER_DETECT (1 << 1) #define MII_BMSR_JABBER_DETECT BIT(1) /** extended register capabilities */ #define MII_BMSR_EXTEND_CAPAB (1 << 0) #define MII_BMSR_EXTEND_CAPAB BIT(0) /* Auto-negotiation Advertisement Register (ANAR) bit definitions */ /* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */ /** next page */ #define MII_ADVERTISE_NEXT_PAGE (1 << 15) #define MII_ADVERTISE_NEXT_PAGE BIT(15) /** link partner acknowledge response */ #define MII_ADVERTISE_LPACK (1 << 14) #define MII_ADVERTISE_LPACK BIT(14) /** remote fault */ #define MII_ADVERTISE_REMOTE_FAULT (1 << 13) #define MII_ADVERTISE_REMOTE_FAULT BIT(13) /** try for asymmetric pause */ #define MII_ADVERTISE_ASYM_PAUSE (1 << 11) #define MII_ADVERTISE_ASYM_PAUSE BIT(11) /** try for pause */ #define MII_ADVERTISE_PAUSE (1 << 10) #define MII_ADVERTISE_PAUSE BIT(10) /** try for 100BASE-T4 support */ #define MII_ADVERTISE_100BASE_T4 (1 << 9) #define MII_ADVERTISE_100BASE_T4 BIT(9) /** try for 100BASE-X full duplex support */ #define MII_ADVERTISE_100_FULL (1 << 8) #define MII_ADVERTISE_100_FULL BIT(8) /** try for 100BASE-X support */ #define MII_ADVERTISE_100_HALF (1 << 7) #define MII_ADVERTISE_100_HALF BIT(7) /** try for 10 Mb/s full duplex support */ #define MII_ADVERTISE_10_FULL (1 << 6) #define MII_ADVERTISE_10_FULL BIT(6) /** try for 10 Mb/s half duplex support */ #define MII_ADVERTISE_10_HALF (1 << 5) #define MII_ADVERTISE_10_HALF BIT(5) /** Selector Field Mask */ #define MII_ADVERTISE_SEL_MASK (0x1F << 0) /** Selector Field */ Loading @@ -140,9 +142,9 @@ /* 1000BASE-T Control Register bit definitions */ /** try for 1000BASE-T full duplex support */ #define MII_ADVERTISE_1000_FULL (1 << 9) #define MII_ADVERTISE_1000_FULL BIT(9) /** try for 1000BASE-T half duplex support */ #define MII_ADVERTISE_1000_HALF (1 << 8) #define MII_ADVERTISE_1000_HALF BIT(8) /** Advertise all speeds */ #define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\ Loading @@ -151,13 +153,13 @@ /* Extended Status Register bit definitions */ /** 1000BASE-X full-duplex capable */ #define MII_ESTAT_1000BASE_X_FULL (1 << 15) #define MII_ESTAT_1000BASE_X_FULL BIT(15) /** 1000BASE-X half-duplex capable */ #define MII_ESTAT_1000BASE_X_HALF (1 << 14) #define MII_ESTAT_1000BASE_X_HALF BIT(14) /** 1000BASE-T full-duplex capable */ #define MII_ESTAT_1000BASE_T_FULL (1 << 13) #define MII_ESTAT_1000BASE_T_FULL BIT(13) /** 1000BASE-T half-duplex capable */ #define MII_ESTAT_1000BASE_T_HALF (1 << 12) #define MII_ESTAT_1000BASE_T_HALF BIT(12) /* MMD Access Control Register (MII_MMD_ACR) Register bit definitions */ /** DEVAD Mask */ Loading
Fin Maaß <f.maass@vogl-electronic.com>Fin Maaß <f.maass@vogl-electronic.com>