Commit d8ab8132 authored by Tomas Galbicka's avatar Tomas Galbicka Committed by Benjamin Cabé
Browse files

boards: Add multicore support on CPU1 for MCXN947 

This commit adds multicore support for MCXN947.
It enables the secondary core CPU1 to boot from flash.

Signed-off-by: default avatarTomas Galbicka <tomas.galbicka@nxp.com>
parent d4d180c2

boards/nxp/frdm_mcxn947/board.cmake

+9 −3
Changes for boards/nxp/frdm_mcxn947/board.cmake: 9 added lines, 3 removed lines.
Original line number Diff line number Diff line
@@ -4,10 +4,14 @@ 
# SPDX-License-Identifier: Apache-2.0

#



if(CONFIG_SOC_MCXN947_CPU0)

if(CONFIG_SOC_MCXN947_CPU0 OR CONFIG_SECOND_CORE_MCUX)

  board_runner_args(jlink "--device=MCXN947_M33_0" "--reset-after-load")

  board_runner_args(linkserver  "--device=MCXN947:FRDM-MCXN947")

  if(CONFIG_SECOND_CORE_MCUX)

    board_runner_args(linkserver  "--core=all")

  else()

    board_runner_args(linkserver  "--core=cm33_core0")

  endif()

  board_runner_args(linkserver  "--override=/device/memory/1/flash-driver=MCXN9xx_S.cfx")

  board_runner_args(linkserver  "--override=/device/memory/1/location=0x10000000")

  # Linkserver v1.4.85 and earlier do not include the secure regions in the
@@ -19,8 +23,10 @@ if(CONFIG_SOC_MCXN947_CPU0) 
  # Define region for peripherals

  board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\

                               \"size\":\"0x00140000\",\"type\":\"RAM\"\}")

else()

  message(FATAL_ERROR "Support for cpu1 not available yet")

elseif(CONFIG_SOC_MCXN947_CPU1)

  board_runner_args(jlink "--device=MCXN947_M33_1" "--reset-after-load")

  board_runner_args(linkserver  "--device=MCXN947:FRDM-MCXN947")

  board_runner_args(linkserver  "--core=cm33_core1")

endif()



# Pyocd support added with the NXP.MCXN947_DFP.17.0.0.pack CMSIS Pack

boards/nxp/frdm_mcxn947/doc/index.rst

+69 −4
Changes for boards/nxp/frdm_mcxn947/doc/index.rst: 69 added lines, 4 removed lines.
Original line number Diff line number Diff line
@@ -103,14 +103,45 @@ The FRDM-MCXN947 board configuration supports the following hardware features: 
| MRT       | on-chip    | counter                             |

+-----------+------------+-------------------------------------+



Dual Core samples

*****************



+-----------+------------------+----------------------+

| Core      | Boot Address     | Comment              |

+===========+==================+======================+

| CPU0      | 0x10000000[992K] | primary core flash   |

+-----------+------------------+----------------------+

| CPU1      | 0x101ce000[200K] | secondary core flash |

+-----------+------------------+----------------------+



+----------+------------------+-----------------------+

| Memory   | Address[Size]    | Comment               |

+==========+==================+=======================+

| srama    | 0x20000000[320k] | CPU0 ram              |

+----------+------------------+-----------------------+

| sramg    | 0x20050000[64k]  | CPU1 ram              |

+----------+------------------+-----------------------+

| sramh    | 0x20060000[32k]  | Shared memory         |

+----------+------------------+-----------------------+



Targets available

==================



The default configuration file

:zephyr_file:`boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig`

only enables the first core.

only enables the first core. CPU0 is the only target that can run standalone.



CPU1 does not work without CPU0 enabling it.



To enable CPU1, create System Build application project and enable the

second core with config :kconfig:option:`CONFIG_SECOND_CORE_MCUX`.



Other hardware features are not currently supported by the port.

Please have a look at some already enabled samples:



- :zephyr_file:`samples/subsys/ipc/ipc_service/static_vrings`

- :zephyr_file:`samples/subsys/ipc/openamp`

- :zephyr_file:`samples/drivers/mbox`

- :zephyr_file:`samples/drivers/mbox_data`



Connections and IOs

===================
@@ -121,9 +152,13 @@ can be used to configure the functionality of a pin. 
+------------+-----------------+----------------------------+

| Name       | Function        | Usage                      |

+============+=================+============================+

| P0_PIO1_8  | UART            | UART RX                    |

| P0_PIO1_8  | UART            | UART RX cpu0               |

+------------+-----------------+----------------------------+

| P1_PIO1_9  | UART            | UART TX cpu0               |

+------------+-----------------+----------------------------+

| P1_PIO1_9  | UART            | UART TX                    |

| P4_PIO4_3  | UART            | UART RX cpu1               |

+------------+-----------------+----------------------------+

| P4_PIO4_2  | UART            | UART TX cpu1               |

+------------+-----------------+----------------------------+



System Clock
@@ -206,6 +241,25 @@ see the following message in the terminal: 
   *** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 ***

   Hello World! frdm_mcxn947/mcxn947/cpu0



Building a dual-core image

--------------------------



The dual-core samples are run using ``frdm_mcxn947/mcxn947/cpu0`` target.



Images built for ``frdm_mcxn947/mcxn947/cpu1`` will be loaded from flash

and executed on the second core when :kconfig:option:`CONFIG_SECOND_CORE_MCUX` is selected.



For an example of building for both cores with System Build, see

:zephyr_file:`samples/subsys/ipc/ipc_service/static_vrings`



Here is an example for the :zephyr:code-sample:`mbox_data` application.



.. zephyr-app-commands::

   :app: zephyr/samples/drivers/mbox_data

   :board: frdm_mcxn947/mcxn947/cpu0

   :goals: flash

   :west-args: --sysbuild



Flashing to QSPI

================
@@ -261,6 +315,14 @@ should see the following message in the terminal: 
   *** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 ***

   Hello World! frdm_mcxn947/mcxn947/cpu0



Debugging a dual-core image

---------------------------



For dual core builds, the secondary core should be placed into a loop,

then a debugger can be attached.

As a reference please see (`AN13264`_, section 4.2.3 for more information).

The reference is for the RT1170 but similar technique can be also used here.



Troubleshooting

===============
@@ -287,3 +349,6 @@ Troubleshooting 


.. _FRDM-MCXN947 Schematics:

   https://www.nxp.com/webapp/Download?colCode=90818-MCXN947SH



.. _AN13264:

   https://www.nxp.com/docs/en/application-note/AN13264.pdf

boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi

+18 −12
Changes for boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi: 18 added lines, 12 removed lines.
Original line number Diff line number Diff line
@@ -132,6 +132,17 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { 
	status = "okay";

};



&sram {

	sramg: memory@20050000 {

		compatible = "mmio-sram";

		reg = <0x20050000 DT_SIZE_K(64)>;

	};

	sramh: memory@20060000 {

		compatible = "mmio-sram";

		reg = <0x20060000 DT_SIZE_K(32)>;

	};

};



&flash {

	partitions {

		compatible = "fixed-partitions";
@@ -147,11 +158,15 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { 
		 */

		slot0_partition: partition@14000 {

			label = "image-0";

			reg = <0x00014000 DT_SIZE_K(984)>;

			reg = <0x00014000 DT_SIZE_K(884)>;

		};

		slot1_partition: partition@10A000 {

		slot1_partition: partition@F1000 {

			label = "image-1";

			reg = <0x0010A000 DT_SIZE_K(984)>;

			reg = <0x000F1000 DT_SIZE_K(884)>;

		};

		cpu1_partition: partition@1CE000 {

			label = "cpu1-image";

			reg = <0x001CE000 DT_SIZE_K(200)>;

		};

		/* storage_partition is placed in WINBOND flash memory*/

	};
@@ -183,15 +198,6 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { 
		cs-setup-time = <3>;

		data-valid-time = <2>;

		column-space = <0>;

		partitions {

			compatible = "fixed-partitions";

			#address-cells = <1>;

			#size-cells = <1>;

			storage_partition: partition@0 {

				label = "storage";

				reg = <0x0 DT_SIZE_M(8)>;

			};

		};

	};

};

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi

+14 −0
Changes for boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi: 14 added lines, 0 removed lines.
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
		zephyr,console = &flexcomm4_lpuart4;

		zephyr,shell-uart = &flexcomm4_lpuart4;

		zephyr,canbus = &flexcan0;

		zephyr,code-cpu1-partition = &cpu1_partition;

	};



	aliases{
@@ -51,6 +52,10 @@ 
	reg = <0x20000000 DT_SIZE_K(320)>;

};



&mbox {

	status = "okay";

};



&gpio4 {

	status = "okay";

};
@@ -129,6 +134,15 @@ 


&w25q64jvssiq {

	status = "okay";

	partitions {

		compatible = "fixed-partitions";

		#address-cells = <1>;

		#size-cells = <1>;

		storage_partition: partition@0 {

			label = "storage";

			reg = <0x0 DT_SIZE_M(8)>;

		};

	};

};



&dac0 {

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.dts

0 → 100644
+72 −0
Changes for boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.dts: 72 added lines, 0 removed lines.
Original line number Diff line number Diff line 
/*

 * Copyright 2024 NXP

 *

 * SPDX-License-Identifier: Apache-2.0

 */



/dts-v1/;



#include <nxp/nxp_mcxn94x.dtsi>

#include "frdm_mcxn947.dtsi"



/ {

	model = "NXP FRDM_N94 board";

	compatible = "nxp,mcxn947", "nxp,mcx";



	cpus {

		/delete-node/ cpu@0;

	};



	chosen {

		zephyr,sram = &sramg;

		zephyr,flash = &flash;

		zephyr,flash-controller = &fmu;

		zephyr,code-partition = &cpu1_partition;

		zephyr,console = &flexcomm2_lpuart2;

		zephyr,shell-uart = &flexcomm2_lpuart2;

	};

};



&flexcomm2 {

	status = "okay";

};



&flexcomm2_lpuart2 {

	status = "okay";

};



&mbox {

	status = "okay";

};



&gpio4 {

	status = "okay";

};



&gpio1 {

	status = "okay";

};



&gpio0 {

	status = "okay";

};



&gpio2 {

	status = "okay";

};



&green_led {

	status = "okay";

};



&red_led {

	status = "okay";

};



&user_button_2 {

	status = "okay";

};



&edma0 {

	status = "okay";

};

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