Commit d85d3df3 authored by Aksel Skauge Mellbye's avatar Aksel Skauge Mellbye Committed by Benjamin Cabé
Browse files

dts: arm: silabs: Add Series 2 TIMER PWM 



Add binding and DT nodes for PWM using the Timer peripheral.

Signed-off-by: default avatarAksel Skauge Mellbye <aksel.mellbye@silabs.com>
parent 6b1c5e97

dts/arm/silabs/xg21/xg21.dtsi

+64 −0
Original line number Diff line number Diff line
@@ -211,6 +211,70 @@ 
			};

		};



		timer0: timer@50048000 {

			compatible = "silabs,series2-timer";

			reg = <0x50048000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <32>;

			interrupts = <6 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer1: timer@5004c000 {

			compatible = "silabs,series2-timer";

			reg = <0x5004c000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <7 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer2: timer@50050000 {

			compatible = "silabs,series2-timer";

			reg = <0x50050000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <8 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer3: timer@50054000 {

			compatible = "silabs,series2-timer";

			reg = <0x50054000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <9 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		usart0: usart@50058000 { /* USART0 */

			compatible = "silabs,usart-uart";

			reg = <0x50058000 0x400>;

dts/arm/silabs/xg22/xg22.dtsi

+80 −0
Original line number Diff line number Diff line
@@ -251,6 +251,86 @@ 
			};

		};



		timer0: timer@50048000 {

			compatible = "silabs,series2-timer";

			reg = <0x50048000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER0 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <32>;

			interrupts = <7 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer1: timer@5004c000 {

			compatible = "silabs,series2-timer";

			reg = <0x5004c000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER1 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <8 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer2: timer@50050000 {

			compatible = "silabs,series2-timer";

			reg = <0x50050000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER2 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <9 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer3: timer@50054000 {

			compatible = "silabs,series2-timer";

			reg = <0x50054000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER3 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <10 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer4: timer@50058000 {

			compatible = "silabs,series2-timer";

			reg = <0x50058000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER4 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <11 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		usart0: usart@5005c000 {

			compatible = "silabs,usart-spi";

			reg = <0x5005C000 0x400>;

dts/arm/silabs/xg23/xg23.dtsi

+80 −0
Original line number Diff line number Diff line
@@ -291,6 +291,86 @@ 
			};

		};



		timer0: timer@50048000 {

			compatible = "silabs,series2-timer";

			reg = <0x50048000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER0 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <32>;

			interrupts = <4 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer1: timer@5004c000 {

			compatible = "silabs,series2-timer";

			reg = <0x5004c000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER1 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <5 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer2: timer@50050000 {

			compatible = "silabs,series2-timer";

			reg = <0x50050000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER2 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <6 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer3: timer@50054000 {

			compatible = "silabs,series2-timer";

			reg = <0x50054000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER3 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <7 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer4: timer@50058000 {

			compatible = "silabs,series2-timer";

			reg = <0x50058000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER4 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <8 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		usart0: usart@5005c000 {

			compatible = "silabs,usart-uart";

			reg = <0x5005C000 0x4000>;

dts/arm/silabs/xg24/xg24.dtsi

+80 −0
Original line number Diff line number Diff line
@@ -281,6 +281,86 @@ 
			};

		};



		timer0: timer@50048000 {

			compatible = "silabs,series2-timer";

			reg = <0x50048000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER0 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <32>;

			interrupts = <4 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer1: timer@5004c000 {

			compatible = "silabs,series2-timer";

			reg = <0x5004c000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER1 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <32>;

			interrupts = <5 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer2: timer@50050000 {

			compatible = "silabs,series2-timer";

			reg = <0x50050000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER2 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <6 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer3: timer@50054000 {

			compatible = "silabs,series2-timer";

			reg = <0x50054000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER3 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <7 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer4: timer@50058000 {

			compatible = "silabs,series2-timer";

			reg = <0x50058000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER4 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <8 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		usart0: usart@5005c000 {

			compatible = "silabs,usart-uart";

			reg = <0x5005C000 0x306c>;

dts/arm/silabs/xg27/xg27.dtsi

+80 −0
Original line number Diff line number Diff line
@@ -261,6 +261,86 @@ 
			};

		};



		timer0: timer@50048000 {

			compatible = "silabs,series2-timer";

			reg = <0x50048000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER0 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <32>;

			interrupts = <10 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer1: timer@5004c000 {

			compatible = "silabs,series2-timer";

			reg = <0x5004c000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER1 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <32>;

			interrupts = <11 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer2: timer@50050000 {

			compatible = "silabs,series2-timer";

			reg = <0x50050000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER2 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <12 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer3: timer@50054000 {

			compatible = "silabs,series2-timer";

			reg = <0x50054000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER3 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <13 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		timer4: timer@50058000 {

			compatible = "silabs,series2-timer";

			reg = <0x50058000 0x4000>;

			channels = <3>;

			clocks = <&cmu CLOCK_TIMER4 CLOCK_BRANCH_EM01GRPACLK>;

			counter-size = <16>;

			interrupts = <14 2>;

			status = "disabled";



			pwm {

				compatible = "silabs,timer-pwm";

				#pwm-cells = <3>;

				status = "disabled";

			};

		};



		usart0: usart@5005c000 {

			compatible = "silabs,usart-spi";

			reg = <0x5005C000 0x400>;

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