Commit d646b9b2 authored by Alain Volmat's avatar Alain Volmat Committed by Benjamin Cabé
Browse files

include: dt-bindings: stm32_clocks: add stm32l4+ bindings header 



On stm32l4+ series, the SAI1 and SAI2 clock source selection fields
are within a different register hence a different binding header
file is introduced to allow proper field usage on those platforms.

Signed-off-by: default avatarAlain Volmat <alain.volmat@foss.st.com>
parent 565bae24

include/zephyr/dt-bindings/clock/stm32l4_clock.h

+0 −2
Original line number Diff line number Diff line
@@ -70,8 +70,6 @@ 
#define I2C4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)

#define DFSDM_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 2, CCIPR2_REG)

#define ADFSDM_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG)

/* #define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG) */

/* #define SAI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG) */

#define DSI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR2_REG)

#define SDMMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG)

#define OSPI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG)

include/zephyr/dt-bindings/clock/stm32l4plus_clock.h

0 → 100644
+22 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2025 STMicroelectronics

 *

 * SPDX-License-Identifier: Apache-2.0

 */

#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4PLUS_CLOCK_H_

#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4PLUS_CLOCK_H_



#include "stm32l4_clock.h"



/*

 * On STM32L4+ series, the SAI1 / SAI2 input clock selection fields

 * are located within the CCIPR2 register instead of the CCIPR register

 */

#undef SAI1_SEL(val)

#undef SAI2_SEL(val)



/** CCIPR2 devices */

#define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG)

#define SAI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG)



#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4PLUS_CLOCK_H_ */

CRA Git | Maintained and supported by SUSTech CRA and CCSE