soc: mimxrt11xx: Allow to override SYS PLL2/3 output divider(s).

To reduce the SEMC clock to a usable speed we had to divide down
the output clock of System PLL2 PFD1. To do this I had to override
the hardcoded defaults. This commit adds the flexibility to
override them in your board files.

Signed-off-by: Bas van Loon <bas@arch-embedded.com>