arch: arm: cortex_m: Use arch_irq_lock instead of a bespoke asm impl (d55ea8db) · Commits · Wenxi XU / zephyr

include/zephyr/arch/arm/error.h

+9 −20

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2013-2014 Wind River Systems, Inc.
		* Copyright (c) 2023 Arm Limited
		*
		* SPDX-License-Identifier: Apache-2.0
		*/
		@@ -23,7 +24,7 @@
		extern "C" {
		#endif

		#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
		#if defined(CONFIG_CPU_CORTEX_M)
		/* ARMv6 will hard-fault if SVC is called with interrupts locked. Just
		* force them unlocked, the thread is in an undefined state anyway
		*
		@@ -33,25 +34,13 @@ extern "C" {
		* Force them unlocked as well.
		*/
		#define ARCH_EXCEPT(reason_p) \
		register uint32_t r0 __asm__("r0") = reason_p; \
		do {\
		arch_irq_unlock(0); \
		__asm__ volatile( \
		"cpsie i\n\t" \
		"svc %[id]\n\t" \
		: \
		: "r" (r0), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \
		: "memory"); \
		} while (false)
		#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
		#define ARCH_EXCEPT(reason_p) do { \
		__asm__ volatile ( \
		"eors.n r0, r0\n\t" \
		"msr BASEPRI, r0\n\t" \
		"mov r0, %[reason]\n\t" \
		"svc %[id]\n\t" \
		: \
		: [reason] "i" (reason_p), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \
		: "memory"); \
		"mov r0, %[_reason]\n" \
		"svc %[id]\n" \
		:: [_reason] "r" (reason_p), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \
		: "r0", "memory"); \
		} while (false)
		#elif defined(CONFIG_ARMV7_R) \|\| defined(CONFIG_AARCH32_ARMV8_R) \
		\|\| defined(CONFIG_ARMV7_A)