soc: arm: Add Broadcom Viper SoC support (d18ae2e9) · Commits · Wenxi XU / zephyr

dts/arm/broadcom/viper-a72.dtsi

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		/*
		* Copyright 2020 Broadcom
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <arm/armv8-a.dtsi>
		#include <dt-bindings/interrupt-controller/arm-gic.h>

		#include "viper-common.dtsi"

		/ {
		cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0>;
		};
		};

		soc {
		gic: interrupt-controller@42700000 {
		compatible = "arm,gic";
		reg = <0x42700000 0x010000>,
		<0x42780000 0x600000>;
		interrupt-controller;
		#interrupt-cells = <4>;
		label = "GIC";
		status = "okay";
		};

		arch_timer: timer {
		compatible = "arm,arm-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_DEFAULT_PRIORITY
		IRQ_TYPE_LEVEL>,
		<GIC_PPI 14 IRQ_DEFAULT_PRIORITY
		IRQ_TYPE_LEVEL>,
		<GIC_PPI 11 IRQ_DEFAULT_PRIORITY
		IRQ_TYPE_LEVEL>,
		<GIC_PPI 10 IRQ_DEFAULT_PRIORITY
		IRQ_TYPE_LEVEL>;
		label = "arch_timer";
		};

		};
		};

		&uart0 {
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 24 IRQ_DEFAULT_PRIORITY
		IRQ_TYPE_LEVEL>;
		};

		&uart1 {
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 181 IRQ_DEFAULT_PRIORITY
		IRQ_TYPE_LEVEL>;
		};

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		/*
		* Copyright 2020 Broadcom
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		/ {
		soc {
		sram0: memory@400000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x00400000 0x80000>;
		};

		uart0: uart@40020000 {
		compatible = "ns16550";
		reg = <0x40020000 0x400>;
		clock-frequency = <25000000>;
		label = "CRMU_UART";
		status = "disabled";
		};

		uart1: uart@48100000 {
		compatible = "ns16550";
		reg = <0x48100000 0x400>;
		clock-frequency = <100000000>;
		label = "CCG_UART0";
		status = "disabled";
		};
		};
		};

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		/*
		* Copyright 2020 Broadcom
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <arm/armv7-m.dtsi>

		#include "viper-common.dtsi"

		/ {
		cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-m7";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;

		mpu: mpu@e000ed90 {
		compatible = "arm,armv7m-mpu";
		reg = <0xe000ed90 0x40>;
		arm,num-mpu-regions = <16>;
		};
		};
		};
		};

		&nvic {
		arm,num-irq-priority-bits = <3>;
		};

		&uart0 {
		interrupts = <1 3>;
		};

		&uart1 {
		interrupts = <197 3>;
		};

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		# SPDX-License-Identifier: Apache-2.0

		description: >
		This is a representation of ARM Cortex-A72 CPU.

		compatible: "arm,cortex-a72"

		include: cpu.yaml

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		# SPDX-License-Identifier: Apache-2.0

		zephyr_include_directories(.)
		zephyr_sources(
		soc.c
		)

		zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)