dts: bindings: flash_controller: Add CS high time to stm32-qspi-nor

The STM32 QUADSPI peripheral allows to configure, in clock cycles, the
duration the chip select signal must stay high between each command sent
to the flash memory controller (QUADSPI_DCR_CSHT).

Currently, this value is set by the flash driver to 1 clock cycle in
single flash mode and 3 clock cycles in dual flash mode. However, the
minimal duration depends on the flash memory (typically 30-50 ns) and
the number of clock cycles on the QSPI's clock frequency. So, adding
this new property allows to select the value of CSHT to match the
requirement of the flash memory used. Also note that in single flash
mode, the current configuration is out-of-spec for most flash memories.

Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>