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Commit ce2d907e authored by Pisit Sawangvonganan's avatar Pisit Sawangvonganan Committed by Benjamin Cabé
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drivers: clock_control: stm32: enable PLL1FRACN setting 



Enables the fractional-N (FRACN) setting for PLL1 in the STM32H5XX
clock driver.
This feature allows achieving a system clock frequency of 250 MHz from
an 8 MHz `clk_hse`.

Signed-off-by: default avatarPisit Sawangvonganan <pisit@ndrsolution.com>
parent db28dbd8
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