boards: arm: mixmrt1040_evk: enable SPI support (cc3ca993) · Commits · Wenxi XU / zephyr

boards/arm/mimxrt1040_evk/doc/index.rst

+14 −0

Changes for boards/arm/mimxrt1040_evk/doc/index.rst: 14 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		@@ -95,6 +95,10 @@ already supported, which can also be re-used on this mimxrt1040_evk board:
		+-----------+------------+-------------------------------------+
		\| ADC \| on-chip \| adc \|
		+-----------+------------+-------------------------------------+
		\| SPI \| on-chip \| spi \|
		+-----------+------------+-------------------------------------+
		\| DMA \| on-chip \| dma \|
		+-----------+------------+-------------------------------------+

		The default configuration can be found in the defconfig file:

		@@ -124,6 +128,16 @@ The MIMXRT1040 SoC has five pairs of pinmux/gpio controllers.
		+---------------+-----------------+---------------------------+
		\| GPIO_AD_B0_15 \| ADC0 IN4 \| ADC0 Input \|
		+---------------+-----------------+---------------------------+
		\| GPIO_SD_B0_02 \| LPSPI1_SDO \| SPI Output \|
		+---------------+-----------------+---------------------------+
		\| GPIO_SD_B0_03 \| LPSPI1_SDI \| SPI Input \|
		+---------------+-----------------+---------------------------+
		\| GPIO_SD_B0_00 \| LPSPI1_SCK \| SPI Clock \|
		+---------------+-----------------+---------------------------+

		.. note::
		In order to use the SPI peripheral on this board, resistors R350, R346,
		and R360 must be populated with zero ohm resistors.

		System Clock
		============

+12 −0

Changes for boards/arm/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi: 12 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		@@ -30,6 +30,18 @@
		};
		};

		/* Note that R350, R346, and R360 must be populated to use SPI */
		pinmux_lpspi1: pinmux_lpspi1 {
		group0 {
		pinmux = <&iomuxc_gpio_sd_b0_02_lpspi1_sdo>,
		<&iomuxc_gpio_sd_b0_03_lpspi1_sdi>,
		<&iomuxc_gpio_sd_b0_00_lpspi1_sck>;
		drive-strength = "r0-6";
		slew-rate = "slow";
		nxp,speed = "100-mhz";
		};
		};

		pinmux_lpuart1: pinmux_lpuart1 {
		group0 {
		pinmux = <&iomuxc_gpio_ad_b0_13_lpuart1_rx>,

+13 −0

Changes for boards/arm/mimxrt1040_evk/mimxrt1040_evk.dts: 13 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		@@ -116,6 +116,19 @@
		pinctrl-names = "default";
		};

		&lpspi1 {
		status = "okay";
		/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
		dmas = <&edma0 0 13>, <&edma0 1 14>;
		dma-names = "rx", "tx";
		pinctrl-0 = <&pinmux_lpspi1>;
		pinctrl-names = "default";
		};

		&edma0 {
		status = "okay";
		};

		/* GPT and Systick are enabled. If power management is enabled, the GPT
		* timer will be used instead of systick, as allows the core clock to
		* be gated.

+1 −0

0 → 100644

+7 −0

Changes for tests/drivers/spi/spi_loopback/boards/mimxrt1040_evk.conf: 7 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		#
		# Copyright 2023 NXP
		#
		# SPDX-License-Identifier: Apache-2.0
		#
		CONFIG_SPI_MCUX_LPSPI_DMA=y
		CONFIG_SPI_ASYNC=n