arch: arm: cortex_m: Apply clang-format on cortex_m related code (caafe238) · Commits · Wenxi XU / zephyr

arch/arm/core/cortex_m/cmse/arm_core_cmse.c

+14 −21

Original line number	Diff line number	Diff line
		@@ -40,8 +40,7 @@ int arm_cmse_addr_readwrite_ok(uint32_t addr, int force_npriv)
		return arm_cmse_addr_read_write_ok(addr, force_npriv, 1);
		}

		static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size,
		int force_npriv, int rw)
		static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size, int force_npriv, int rw)
		{
		int flags = 0;

		@@ -112,8 +111,7 @@ int arm_cmse_addr_is_secure(uint32_t addr)
		return addr_info.flags.secure;
		}

		static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr,
		int force_npriv, int rw)
		static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr, int force_npriv, int rw)
		{
		cmse_address_info_t addr_info;
		if (force_npriv) {
		@@ -122,8 +120,7 @@ static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr,
		addr_info = cmse_TTA((void *)addr);
		}

		return rw ? addr_info.flags.nonsecure_readwrite_ok :
		addr_info.flags.nonsecure_read_ok;
		return rw ? addr_info.flags.nonsecure_readwrite_ok : addr_info.flags.nonsecure_read_ok;
		}

		int arm_cmse_addr_nonsecure_read_ok(uint32_t addr, int force_npriv)
		@@ -156,18 +153,14 @@ static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t s
		}
		}

		int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size,
		int force_npriv)
		int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, int force_npriv)
		{
		return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size,
		force_npriv, 0);
		return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 0);
		}

		int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size,
		int force_npriv)
		int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int force_npriv)
		{
		return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size,
		force_npriv, 1);
		return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 1);
		}

		#endif /* CONFIG_ARM_SECURE_FIRMWARE */

arch/arm/core/cortex_m/cpu_idle.c

+21 −17

Original line number	Diff line number	Diff line
		@@ -30,11 +30,14 @@ void z_arm_cpu_idle_init(void)
		#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
		#define ON_EXIT_IDLE_HOOK SOC_ON_EXIT_CPU_IDLE
		#else
		#define ON_EXIT_IDLE_HOOK do {} while (false)
		#define ON_EXIT_IDLE_HOOK \
		do { \
		} while (false)
		#endif

		#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
		#define SLEEP_IF_ALLOWED(wait_instr) do { \
		#define SLEEP_IF_ALLOWED(wait_instr) \
		do { \
		/* Skip the wait instr if on_enter_cpu_idle returns false */ \
		if (z_arm_on_enter_cpu_idle()) { \
		/* Wait for all memory transaction to complete */ \
		@@ -46,7 +49,8 @@ void z_arm_cpu_idle_init(void)
		} \
		} while (false)
		#else
		#define SLEEP_IF_ALLOWED(wait_instr) do { \
		#define SLEEP_IF_ALLOWED(wait_instr) \
		do { \
		__DSB(); \
		wait_instr(); \
		ON_EXIT_IDLE_HOOK; \

arch/arm/core/cortex_m/debug.c

+11 −22

Original line number	Diff line number	Diff line
		@@ -81,20 +81,12 @@ int z_arm_debug_enable_null_pointer_detection(void)
		DWT->COMP0 = 0;
		DWT->COMP1 = CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1;

		DWT->FUNCTION0 =
		((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk)
		\|
		((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk)
		\|
		((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk)
		;
		DWT->FUNCTION1 =
		((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk)
		\|
		((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk)
		\|
		((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk)
		;
		DWT->FUNCTION0 = ((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) \|
		((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) \|
		((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk);
		DWT->FUNCTION1 = ((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) \|
		((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) \|
		((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk);
		#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)

		/* ASSERT that we have the comparator needed for the implementation */
		@@ -106,13 +98,10 @@ int z_arm_debug_enable_null_pointer_detection(void)
		/* Use comparator 0, R/W access check */
		DWT->COMP0 = 0;

		DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) &
		DWT_FUNCTION_FUNCTION_Msk;

		DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) & DWT_FUNCTION_FUNCTION_Msk;

		/* Set mask according to the desired size */
		DWT->MASK0 = 32 - __builtin_clzl(
		CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1);
		DWT->MASK0 = 32 - __builtin_clzl(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1);
		#endif

		return 0;

arch/arm/core/cortex_m/fault.c

+53 −80

Original line number	Diff line number	Diff line
		@@ -55,14 +55,11 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
		#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
		/* helpers to access memory/bus/usage faults */
		#define SCB_CFSR_MEMFAULTSR \
		(uint32_t)((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) \
		>> SCB_CFSR_MEMFAULTSR_Pos)
		(uint32_t)((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) >> SCB_CFSR_MEMFAULTSR_Pos)
		#define SCB_CFSR_BUSFAULTSR \
		(uint32_t)((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) \
		>> SCB_CFSR_BUSFAULTSR_Pos)
		(uint32_t)((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) >> SCB_CFSR_BUSFAULTSR_Pos)
		#define SCB_CFSR_USGFAULTSR \
		(uint32_t)((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) \
		>> SCB_CFSR_USGFAULTSR_Pos)
		(uint32_t)((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) >> SCB_CFSR_USGFAULTSR_Pos)
		#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */

		/**
		@@ -103,8 +100,8 @@ static void fault_show(const struct arch_esf *esf, int fault)
		PR_EXC("Fault! EXC #%d", fault);

		#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
		PR_EXC("MMFSR: 0x%x, BFSR: 0x%x, UFSR: 0x%x", SCB_CFSR_MEMFAULTSR,
		SCB_CFSR_BUSFAULTSR, SCB_CFSR_USGFAULTSR);
		PR_EXC("MMFSR: 0x%x, BFSR: 0x%x, UFSR: 0x%x", SCB_CFSR_MEMFAULTSR, SCB_CFSR_BUSFAULTSR,
		SCB_CFSR_USGFAULTSR);
		#if defined(CONFIG_ARM_SECURE_FIRMWARE)
		PR_EXC("SFSR: 0x%x", SAU->SFSR);
		#endif /* CONFIG_ARM_SECURE_FIRMWARE */
		@@ -127,9 +124,7 @@ static void fault_show(const struct arch_esf *esf, int fault)
		#ifdef CONFIG_USERSPACE
		Z_EXC_DECLARE(z_arm_user_string_nlen);

		static const struct z_exc_handle exceptions[] = {
		Z_EXC_HANDLE(z_arm_user_string_nlen)
		};
		static const struct z_exc_handle exceptions[] = {Z_EXC_HANDLE(z_arm_user_string_nlen)};
		#endif

		/* Perform an assessment whether an MPU fault shall be
		@@ -168,8 +163,7 @@ static bool memory_fault_recoverable(struct arch_esf *esf, bool synchronous)
		#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)

		#if defined(CONFIG_MPU_STACK_GUARD) \|\| defined(CONFIG_USERSPACE)
		uint32_t z_check_thread_stack_fail(const uint32_t fault_addr,
		const uint32_t psp);
		uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp);
		#endif /* CONFIG_MPU_STACK_GUARD \|\| defined(CONFIG_USERSPACE) */

		/**
		@@ -180,8 +174,7 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr,
		*
		* @return error code to identify the fatal error reason
		*/
		static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault,
		bool *recoverable)
		static uint32_t mem_manage_fault(struct arch_esf esf, int from_hard_fault, bool recoverable)
		{
		uint32_t reason = K_ERR_ARM_MEM_GENERIC;
		uint32_t mmfar = -EINVAL;
		@@ -226,8 +219,7 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault,
		#if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
		if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
		reason = K_ERR_ARM_MEM_FP_LAZY_STATE_PRESERVATION;
		PR_FAULT_INFO(
		" Floating-point lazy state preservation error");
		PR_FAULT_INFO(" Floating-point lazy state preservation error");
		}
		#endif /* CONFIG_ARMV7_M_ARMV8_M_FP */

		@@ -244,8 +236,7 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault,
		* Data Access Violation errors may or may not be caused by
		* thread stack overflows.
		*/
		if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) \|\|
		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
		if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) \|\| (SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
		#if defined(CONFIG_MPU_STACK_GUARD) \|\| defined(CONFIG_USERSPACE)
		/* MemManage Faults are always banked between security
		* states. Therefore, we can safely assume the fault
		@@ -265,8 +256,8 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault,
		* handle the case of 'mmfar' holding the -EINVAL value.
		*/
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
		uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
		((uint32_t) &esf[0]));
		uint32_t min_stack_ptr =
		z_check_thread_stack_fail(mmfar, ((uint32_t)&esf[0]));

		if (min_stack_ptr) {
		/* When MemManage Stacking Error has occurred,
		@@ -409,12 +400,9 @@ static int bus_fault(struct arch_esf esf, int from_hard_fault, bool recoverabl
		PR_FAULT_INFO(" NXP MPU error, port %d", i);
		PR_FAULT_INFO(" Mode: %s, %s Address: 0x%x",
		edr & BIT(2) ? "Supervisor" : "User",
		edr & BIT(1) ? "Data" : "Instruction",
		ear);
		PR_FAULT_INFO(
		" Type: %s, Master: %d, Regions: 0x%x",
		edr & BIT(0) ? "Write" : "Read",
		EMN(edr), EACD(edr));
		edr & BIT(1) ? "Data" : "Instruction", ear);
		PR_FAULT_INFO(" Type: %s, Master: %d, Regions: 0x%x",
		edr & BIT(0) ? "Write" : "Read", EMN(edr), EACD(edr));

		/* When stack protection is enabled, we need to assess
		* if the memory violation error is a stack corruption.
		@@ -437,8 +425,7 @@ static int bus_fault(struct arch_esf esf, int from_hard_fault, bool recoverabl
		*/
		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
		uint32_t min_stack_ptr =
		z_check_thread_stack_fail(ear,
		((uint32_t) &esf[0]));
		z_check_thread_stack_fail(ear, ((uint32_t)&esf[0]));

		if (min_stack_ptr) {
		/* When BusFault Stacking Error
		@@ -468,16 +455,14 @@ static int bus_fault(struct arch_esf esf, int from_hard_fault, bool recoverabl
		*/
		__set_PSP(min_stack_ptr);

		reason =
		K_ERR_STACK_CHK_FAIL;
		reason = K_ERR_STACK_CHK_FAIL;
		break;
		}
		}
		#else
		(void)ear;
		__ASSERT(0,
		"Stacking error without stack guard"
		"or User-mode support");
		"Stacking error without stack guard or User-mode support");
		#endif /* CONFIG_MPU_STACK_GUARD \|\| CONFIG_USERSPACE */
		}
		}
		@@ -617,8 +602,7 @@ static void debug_monitor(struct arch_esf esf, bool recoverable)
		{
		*recoverable = false;

		PR_FAULT_INFO(
		"*** Debug monitor exception ***");
		PR_FAULT_INFO("*** Debug monitor exception ***");

		#if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT)
		if (!z_arm_debug_monitor_event_error_check()) {
		@@ -759,12 +743,10 @@ static uint32_t hard_fault(struct arch_esf esf, bool recoverable)
		reason = secure_fault(esf);
		#endif /* CONFIG_ARM_SECURE_FIRMWARE */
		} else {
		__ASSERT(0,
		"Fault escalation without FSR info");
		__ASSERT(0, "Fault escalation without FSR info");
		}
		} else {
		__ASSERT(0,
		"HardFault without HFSR info"
		__ASSERT(0, "HardFault without HFSR info"
		" Shall never occur");
		}
		#else
		@@ -786,8 +768,7 @@ static void reserved_exception(const struct arch_esf *esf, int fault)
		ARG_UNUSED(esf);

		PR_FAULT_INFO("*** %s %d) ***",
		fault < 16 ? "Reserved Exception (" : "Spurious interrupt (IRQ ",
		fault - 16);
		fault < 16 ? "Reserved Exception (" : "Spurious interrupt (IRQ ", fault - 16);
		}

		/* Handler function for ARM fault conditions. */
		@@ -879,7 +860,6 @@ static void secure_stack_dump(const struct arch_esf *secure_esf)
		sec_ret_addr = *top_of_sec_stack;
		}
		PR_FAULT_INFO(" S instruction address: 0x%x", sec_ret_addr);

		}
		#define SECURE_STACK_DUMP(esf) secure_stack_dump(esf)
		#else
		@@ -907,8 +887,7 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_

		*nested_exc = false;

		if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
		EXC_RETURN_INDICATOR_PREFIX) {
		if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) != EXC_RETURN_INDICATOR_PREFIX) {
		/* Invalid EXC_RETURN value. This is a fatal error. */
		return NULL;
		}
		@@ -988,8 +967,7 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_
		/* The processor has a single execution state.
		* We verify that the Thread mode is using PSP.
		*/
		if ((exc_return & EXC_RETURN_MODE_THREAD) &&
		(!(exc_return & EXC_RETURN_SPSEL_PROCESS))) {
		if ((exc_return & EXC_RETURN_MODE_THREAD) && (!(exc_return & EXC_RETURN_SPSEL_PROCESS))) {
		PR_EXC("SPSEL in thread mode does not indicate PSP");
		return NULL;
		}
		@@ -1041,8 +1019,7 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_
		* @param callee_regs Callee-saved registers (R4-R11, PSP)
		*
		*/
		void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
		_callee_saved_t *callee_regs)
		void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, _callee_saved_t *callee_regs)
		{
		uint32_t reason = K_ERR_CPU_EXCEPTION;
		int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
		@@ -1061,8 +1038,7 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
		* as argument to the remainder of the fault handling process.
		*/
		esf = get_esf(msp, psp, exc_return, &nested_exc);
		__ASSERT(esf != NULL,
		"ESF could not be retrieved successfully. Shall never occur.");
		__ASSERT(esf != NULL, "ESF could not be retrieved successfully. Shall never occur.");

		z_arm_set_fault_sp(esf, exc_return);

		@@ -1081,10 +1057,7 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
		*/
		memcpy(&esf_copy, esf, offsetof(struct arch_esf, extra_info));
		esf_copy.extra_info = (struct __extra_esf_info){
		.callee = callee_regs,
		.exc_return = exc_return,
		.msp = msp
		};
		.callee = callee_regs, .exc_return = exc_return, .msp = msp};
		#endif /* CONFIG_EXTRA_EXCEPTION_INFO */

		/* Overwrite stacked IPSR to mark a nested exception,

arch/arm/core/cortex_m/fpu.c

+8 −10

Original line number	Diff line number	Diff line
		@@ -23,11 +23,10 @@ void z_arm_save_fp_context(struct fpu_ctx_full *buffer)

		if (CONTROL & CONTROL_FPCA_Msk) {
		/* Store caller-saved and callee-saved FP registers. */
		__asm__ volatile(
		"vstmia %0, {s0-s15}\n"
		"vstmia %1, {s16-s31}\n"
		:: "r" (buffer->caller_saved), "r" (buffer->callee_saved) :
		);
		__asm__ volatile("vstmia %0, {s0-s15}\n"
		"vstmia %1, {s16-s31}\n" ::"r"(buffer->caller_saved),
		"r"(buffer->callee_saved)
		:);

		buffer->fpscr = __get_FPSCR();
		buffer->ctx_saved = true;
		@@ -55,11 +54,10 @@ void z_arm_restore_fp_context(const struct fpu_ctx_full *buffer)
		/* Restore FP state. */
		__set_FPSCR(buffer->fpscr);

		__asm__ volatile(
		"vldmia %0, {s0-s15}\n"
		"vldmia %1, {s16-s31}\n"
		:: "r" (buffer->caller_saved), "r" (buffer->callee_saved) :
		);
		__asm__ volatile("vldmia %0, {s0-s15}\n"
		"vldmia %1, {s16-s31}\n" ::"r"(buffer->caller_saved),
		"r"(buffer->callee_saved)
		:);
		}
		#endif
		}

Admin message