soc: silabs: Add support for additional BG22 SoCs (ca8d9094) · Commits · Wenxi XU / zephyr

dts/arm/silabs/xg22/efr32bg22c222f352gm32.dtsi

0 → 100644

+25 −0

Changes for dts/arm/silabs/xg22/efr32bg22c222f352gm32.dtsi: 25 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2021 Sateesh Kotapati
		* Copyright (c) 2025 Silicon Laboratories Inc.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <silabs/xg22/efr32bg22.dtsi>
		#include <mem.h>

		/ {
		soc {
		compatible = "silabs,efr32bg22c222f352gm32", "silabs,efr32bg22", "silabs,xg22",
		"silabs,efr32", "simple-bus";
		model = "Silicon Labs EFR32BG22C222F352GM32 SoC";
		};
		};

		&flash0 {
		reg = <0x0 DT_SIZE_K(352)>;
		};

		&sram0 {
		reg = <0x20000000 DT_SIZE_K(32)>;
		};

0 → 100644

+25 −0

Changes for dts/arm/silabs/xg22/efr32bg22c222f352gm40.dtsi: 25 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2021 Sateesh Kotapati
		* Copyright (c) 2025 Silicon Laboratories Inc.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <silabs/xg22/efr32bg22.dtsi>
		#include <mem.h>

		/ {
		soc {
		compatible = "silabs,efr32bg22c222f352gm40", "silabs,efr32bg22", "silabs,xg22",
		"silabs,efr32", "simple-bus";
		model = "Silicon Labs EFR32BG22C222F352GM40 SoC";
		};
		};

		&flash0 {
		reg = <0x0 DT_SIZE_K(352)>;
		};

		&sram0 {
		reg = <0x20000000 DT_SIZE_K(32)>;
		};

0 → 100644

+25 −0

Changes for dts/arm/silabs/xg22/efr32bg22c222f352gn32.dtsi: 25 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2021 Sateesh Kotapati
		* Copyright (c) 2025 Silicon Laboratories Inc.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <silabs/xg22/efr32bg22.dtsi>
		#include <mem.h>

		/ {
		soc {
		compatible = "silabs,efr32bg22c222f352gn32", "silabs,efr32bg22", "silabs,xg22",
		"silabs,efr32", "simple-bus";
		model = "Silicon Labs EFR32BG22C222F352GN32 SoC";
		};
		};

		&flash0 {
		reg = <0x0 DT_SIZE_K(352)>;
		};

		&sram0 {
		reg = <0x20000000 DT_SIZE_K(32)>;
		};

0 → 100644

+25 −0

Changes for dts/arm/silabs/xg22/efr32bg22c224f512gm32.dtsi: 25 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2021 Sateesh Kotapati
		* Copyright (c) 2025 Silicon Laboratories Inc.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <silabs/xg22/efr32bg22.dtsi>
		#include <mem.h>

		/ {
		soc {
		compatible = "silabs,efr32bg22c224f512gm32", "silabs,efr32bg22", "silabs,xg22",
		"silabs,efr32", "simple-bus";
		model = "Silicon Labs EFR32BG22C224F512GM32 SoC";
		};
		};

		&flash0 {
		reg = <0x0 DT_SIZE_K(512)>;
		};

		&sram0 {
		reg = <0x20000000 DT_SIZE_K(32)>;
		};

0 → 100644

+25 −0

Changes for dts/arm/silabs/xg22/efr32bg22c224f512gm40.dtsi: 25 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2021 Sateesh Kotapati
		* Copyright (c) 2025 Silicon Laboratories Inc.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <silabs/xg22/efr32bg22.dtsi>
		#include <mem.h>

		/ {
		soc {
		compatible = "silabs,efr32bg22c224f512gm40", "silabs,efr32bg22", "silabs,xg22",
		"silabs,efr32", "simple-bus";
		model = "Silicon Labs EFR32BG22C224F512GM40 SoC";
		};
		};

		&flash0 {
		reg = <0x0 DT_SIZE_K(512)>;
		};

		&sram0 {
		reg = <0x20000000 DT_SIZE_K(32)>;
		};