Commit c8dbb971 authored by Vinayak Kariappa Chettimada's avatar Vinayak Kariappa Chettimada Committed by Fabio Baltieri
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tests: bsim: hci_uart: Fix execution timeout



Fix execution timeout to be atleast the simulation
length of the tests.

Signed-off-by: default avatarVinayak Kariappa Chettimada <vich@nordicsemi.no>
parent ff914083
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+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
# connected over UART. The controller is the HCI UART sample.
simulation_id="basic_conn_split_hci_uart"
verbosity_level=2
EXECUTE_TIMEOUT=10
EXECUTE_TIMEOUT=20

cd ${BSIM_OUT_PATH}/bin

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
# connected over UART. The controller is the HCI UART async sample.
simulation_id="basic_conn_split_hci_uart_async"
verbosity_level=2
EXECUTE_TIMEOUT=10
EXECUTE_TIMEOUT=20

cd ${BSIM_OUT_PATH}/bin