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Commit c7b55b4e authored by Francois Ramu's avatar Francois Ramu Committed by Maureen Helm
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dts: arm: stm32g0 has a APB peripheral bus clock on 2 registers 



The stm32G0 device has a one APB peripheral clock bus
but splitted on two RCC registers: RCC_ABPENR1 and RCC_ABPENR2
Peripherals are on one or the other.

Signed-off-by: default avatarFrancois Ramu <francois.ramu@st.com>
parent e11d82ba
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