Commit c7b55b4e authored by Francois Ramu's avatar Francois Ramu Committed by Maureen Helm
Browse files

dts: arm: stm32g0 has a APB peripheral bus clock on 2 registers 



The stm32G0 device has a one APB peripheral clock bus
but splitted on two RCC registers: RCC_ABPENR1 and RCC_ABPENR2
Peripherals are on one or the other.

Signed-off-by: default avatarFrancois Ramu <francois.ramu@st.com>
parent e11d82ba

dts/arm/st/g0/stm32g0.dtsi

+7 −7
Original line number Diff line number Diff line
@@ -186,7 +186,7 @@ 
		usart1: serial@40013800 {

			compatible = "st,stm32-usart", "st,stm32-uart";

			reg = <0x40013800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;

			resets = <&rctl STM32_RESET(APB1H, 14U)>;

			interrupts = <27 0>;

			status = "disabled";
@@ -215,7 +215,7 @@ 
		timers1: timers@40012c00 {

			compatible = "st,stm32-timers";

			reg = <0x40012C00 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;

			resets = <&rctl STM32_RESET(APB1H, 11U)>;

			interrupts = <13 0>, <14 0>;

			interrupt-names = "brk_up_trg_com", "cc";
@@ -249,7 +249,7 @@ 
		timers14: timers@40002000 {

			compatible = "st,stm32-timers";

			reg = <0x40002000 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00008000>;

			resets = <&rctl STM32_RESET(APB1H, 15U)>;

			interrupts = <19 0>;

			interrupt-names = "global";
@@ -266,7 +266,7 @@ 
		timers16: timers@40014400 {

			compatible = "st,stm32-timers";

			reg = <0x40014400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;

			resets = <&rctl STM32_RESET(APB1H, 17U)>;

			interrupts = <21 0>;

			interrupt-names = "global";
@@ -283,7 +283,7 @@ 
		timers17: timers@40014800 {

			compatible = "st,stm32-timers";

			reg = <0x40014800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;

			resets = <&rctl STM32_RESET(APB1H, 18U)>;

			interrupts = <22 0>;

			interrupt-names = "global";
@@ -326,7 +326,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40013000 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00001000>;

			interrupts = <25 0>;

			status = "disabled";

		};
@@ -344,7 +344,7 @@ 
		adc1: adc@40012400 {

			compatible = "st,stm32-adc";

			reg = <0x40012400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>;

			interrupts = <12 0>;

			status = "disabled";

			vref-mv = <3300>;

dts/arm/st/g0/stm32g051.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
		timers15: timers@40014000 {

			compatible = "st,stm32-timers";

			reg = <0x40014000 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;

			resets = <&rctl STM32_RESET(APB1H, 16U)>;

			interrupts = <20 0>;

			interrupt-names = "global";

include/zephyr/dt-bindings/clock/stm32g0_clock.h

+2 −2
Original line number Diff line number Diff line
@@ -10,10 +10,10 @@ 
#define STM32_CLOCK_BUS_IOP     0x034

#define STM32_CLOCK_BUS_AHB1    0x038

#define STM32_CLOCK_BUS_APB1    0x03c

#define STM32_CLOCK_BUS_APB2    0x040

#define STM32_CLOCK_BUS_APB1_2  0x040



#define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_IOP

#define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB2

#define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB1_2



/** Domain clocks */

/* RM0444, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */

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