soc: microchip: mec: Add new HAL based MEC5 family chips (c6e3bc32) · Commits · Wenxi XU / zephyr

modules/Kconfig.microchip

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		@@ -7,3 +7,6 @@ config HAS_MEC_HAL

		config HAS_MPFS_HAL
		bool "Microchip MPFS HAL drivers support"

		config HAS_MEC5_HAL
		bool "Microchip MEC5 HAL drivers support"

soc/microchip/mec/Kconfig

+49 −0

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		@@ -8,6 +8,7 @@ if SOC_FAMILY_MICROCHIP_MEC

		menuconfig MCHP_MEC_UNSIGNED_HEADER
		bool "Create an unsigned output binary with MCHP MEC binary header"
		depends on SOC_SERIES_MEC172X
		help
		On Microchip MEC series chip, the ROM code loads firmware image from flash
		to RAM using a TAG to locate a Header which specifies the location and
		@@ -210,6 +211,54 @@ config MCHP_HEADER_VERBOSE_OUTPUT

		endif # MCHP_MEC_UNSIGNED_HEADER

		# Common debug configuration
		choice
		prompt "MEC debug interface general configuration"
		default SOC_MEC_DEBUG_AND_TRACING
		depends on SOC_SERIES_MEC174X \|\| SOC_SERIES_MEC175X \|\| SOC_SERIES_MECH172X
		help
		Select Debug SoC interface support for MEC SoC family

		config SOC_MEC_DEBUG_DISABLED
		bool "Disable debug support"
		help
		Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST#
		pin is ignored. All other JTAG pins can be used as GPIOs
		or other non-JTAG alternate functions.

		config SOC_MEC_DEBUG_WITHOUT_TRACING
		bool "Debug support via Serial wire debug"
		help
		JTAG port in SWD mode.

		config SOC_MEC_DEBUG_AND_TRACING
		bool "Debug support via Serial wire debug with tracing enabled"
		help
		JTAG port is enabled in SWD mode.
		endchoice

		choice
		prompt "MEC debug interface trace configuration"
		default SOC_MEC_DEBUG_AND_SWV_TRACING
		depends on SOC_MEC_DEBUG_AND_TRACING
		help
		Select tracing mode for debug interface

		config SOC_MEC_DEBUG_AND_ETM_TRACING
		bool "Debug support via Serial wire debug"
		help
		JTAG port in SWD mode and ETM as tracing method.
		ETM re-assigns 5 pins for clock and 4-bit data bus.
		Check data sheet for functions shared with ETM.

		config SOC_MEC_DEBUG_AND_SWV_TRACING
		bool "debug support via Serial Wire Debug and Viewer"
		help
		JTAG port in SWD mode and SWV as tracing method.
		Check data sheet for functions shared with SWD and SWV pins.
		endchoice

		# common processor clock divider configuration
		config SOC_MEC_PROC_CLK_DIV
		int "PROC_CLK_DIV"
		default 1

soc/microchip/mec/common/CMakeLists.txt

+3 −0

Original line number	Diff line number	Diff line
		@@ -4,6 +4,9 @@ zephyr_include_directories(.)
		zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_MEC172X
		soc_i2c.c
		)
		zephyr_library_sources_ifdef(CONFIG_HAS_MEC5_HAL
		soc_cmn_init.c
		)

		if (DEFINED CONFIG_MCHP_HEADER_VERBOSE_OUTPUT)
		set(MCHP_HEADER_VERBOSE_OPTION "-v")

soc/microchip/mec/common/soc_cmn_init.c

0 → 100644

+41 −0

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		/*
		* Copyright (c) 2024 Microchip Technology Inc.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <zephyr/device.h>
		#include <zephyr/init.h>
		#include <zephyr/kernel.h>
		#include <soc.h>
		#include <mec_ecia_api.h>
		#include <mec_ecs_api.h>

		static void mec5_soc_init_debug_interface(void)
		{
		#if defined(CONFIG_SOC_MEC_DEBUG_DISABLED)
		mec_ecs_etm_pins(ECS_ETM_PINS_DISABLE);
		mec_ecs_debug_port(MEC_DEBUG_MODE_DISABLE);
		#else
		#if defined(SOC_MEC_DEBUG_WITHOUT_TRACING)
		mec_ecs_etm_pins(ECS_ETM_PINS_DISABLE);
		mec_ecs_debug_port(MEC_DEBUG_MODE_SWD);
		#elif defined(SOC_MEC_DEBUG_AND_TRACING)
		#if defined(SOC_MEC_DEBUG_AND_ETM_TRACING)
		mec_ecs_etm_pins(ECS_ETM_PINS_DISABLE);
		mec_ecs_debug_port(MEC_DEBUG_MODE_SWD_SWV);
		#elif defined(CONFIG_SOC_MEC_DEBUG_AND_ETM_TRACING)
		mec_ecs_debug_port(MEC_DEBUG_MODE_SWD);
		mec_ecs_etm_pins(ECS_ETM_PINS_ENABLE);
		#endif
		#endif
		#endif
		}

		int mec5_soc_common_init(void)
		{
		mec5_soc_init_debug_interface();
		mec_ecia_init(MEC5_ECIA_DIRECT_BITMAP, 1, 0);

		return 0;
		}

soc/microchip/mec/common/soc_cmn_init.h

0 → 100644

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		/*
		* Copyright (c) 2024 Microchip Technology Inc.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#ifndef __MEC5_SOC_CMN_INIT_H
		#define __MEC5_SOC_CMN_INIT_H

		#ifndef _ASMLANGUAGE

		int mec5_soc_common_init(void);

		#endif

		#endif

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