Commit c1dd8ff8 authored by Maureen Helm's avatar Maureen Helm Committed by Anas Nashif
Browse files

arm: nxp: mpu: Fix off-by-1 error in region index calculation 



Both the ARM and NXP MPU drivers incorrectly calculated the region index
by assuming the region type (e.g., THREAD_STACK_GUARD_REGION) was
zero-indexed, when in reality it is one-indexed. This had the effect of
wasting one region.

Signed-off-by: default avatarMaureen Helm <maureen.helm@nxp.com>
parent 85c974ab

arch/arm/core/cortex_m/mpu/arm_mpu.c

+5 −3
Original line number Diff line number Diff line
@@ -108,10 +108,12 @@ void arm_core_mpu_configure(u8_t type, u32_t base, u32_t size) 
{

	SYS_LOG_DBG("Region info: 0x%x 0x%x", base, size);

	/*

	 * The new MPU regions are are allocated per type after the statically

	 * configured regions.

	 * The new MPU regions are allocated per type after the statically

	 * configured regions. The type is one-indexed rather than

	 * zero-indexed, therefore we need to subtract by one to get the region

	 * index.

	 */

	u32_t region_index = mpu_config.num_regions + type;

	u32_t region_index = mpu_config.num_regions + type - 1;

	u32_t region_attr = _get_region_attr_by_type(type, size);



	/* ARM MPU supports up to 16 Regions */

arch/arm/core/cortex_m/mpu/nxp_mpu.c

+5 −3
Original line number Diff line number Diff line
@@ -120,10 +120,12 @@ void arm_core_mpu_configure(u8_t type, u32_t base, u32_t size) 
{

	SYS_LOG_DBG("Region info: 0x%x 0x%x", base, size);

	/*

	 * The new MPU regions are are allocated per type after the statically

	 * configured regions.

	 * The new MPU regions are allocated per type after the statically

	 * configured regions. The type is one-indexed rather than

	 * zero-indexed, therefore we need to subtract by one to get the region

	 * index.

	 */

	u32_t region_index = mpu_config.num_regions + type;

	u32_t region_index = mpu_config.num_regions + type - 1;

	u32_t region_attr = _get_region_attr_by_type(type);

	u32_t last_region = _get_num_regions() - 1;

CRA Git | Maintained and supported by SUSTech CRA and CCSE