Commit bfa6c32e authored by Fabrice DJIATSA's avatar Fabrice DJIATSA Committed by Fabio Baltieri
Browse files

divers: adc: update adc driver to integrate stm32u0 



add u0 config_soc conditions in adc driver to handle
news peripherals.

Signed-off-by: default avatarFabrice DJIATSA <fabrice.djiatsa-ext@st.com>
parent 293eb22d

drivers/adc/adc_stm32.c

+5 −0
Original line number Diff line number Diff line
@@ -454,6 +454,7 @@ static void adc_stm32_disable(ADC_TypeDef *adc) 
	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc) && \

	!defined(CONFIG_SOC_SERIES_STM32G0X) && \

	!defined(CONFIG_SOC_SERIES_STM32L0X) && \

	!defined(CONFIG_SOC_SERIES_STM32U0X) && \

	!defined(CONFIG_SOC_SERIES_STM32WBAX) && \

	!defined(CONFIG_SOC_SERIES_STM32WLX)

	if (LL_ADC_INJ_IsConversionOngoing(adc)) {
@@ -532,8 +533,10 @@ static void adc_stm32_calibration_start(const struct device *dev) 
	DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) || \

	defined(CONFIG_SOC_SERIES_STM32G0X) || \

	defined(CONFIG_SOC_SERIES_STM32L0X) || \

	defined(CONFIG_SOC_SERIES_STM32U0X) || \

	defined(CONFIG_SOC_SERIES_STM32WLX) || \

	defined(CONFIG_SOC_SERIES_STM32WBAX)



	LL_ADC_StartCalibration(adc);

#elif defined(CONFIG_SOC_SERIES_STM32U5X)

	if (adc != ADC4) {
@@ -580,6 +583,7 @@ static int adc_stm32_calibrate(const struct device *dev) 
	defined(CONFIG_SOC_SERIES_STM32G0X) || \

	defined(CONFIG_SOC_SERIES_STM32H7RSX) || \

	defined(CONFIG_SOC_SERIES_STM32L0X) || \

	defined(CONFIG_SOC_SERIES_STM32U0X) || \

	defined(CONFIG_SOC_SERIES_STM32WBAX) || \

	defined(CONFIG_SOC_SERIES_STM32WLX)

	/* Make sure DMA is disabled before starting calibration */
@@ -1384,6 +1388,7 @@ static int adc_stm32_set_clock(const struct device *dev) 
#elif defined(CONFIG_SOC_SERIES_STM32C0X) || \

	defined(CONFIG_SOC_SERIES_STM32G0X) || \

	defined(CONFIG_SOC_SERIES_STM32L0X) || \

	defined(CONFIG_SOC_SERIES_STM32U0X) || \

	(defined(CONFIG_SOC_SERIES_STM32WBX) && defined(ADC_SUPPORT_2_5_MSPS)) || \

	defined(CONFIG_SOC_SERIES_STM32WLX)

	if ((config->clk_prescaler == LL_ADC_CLOCK_SYNC_PCLK_DIV1) ||

CRA Git | Maintained and supported by SUSTech CRA and CCSE