Commit bc8524eb authored by Stephanos Ioannidis's avatar Stephanos Ioannidis Committed by Ioannis Glaropoulos
Browse files

arch: arm: Rewrite Cortex-R reset vector function. 



This commit addresses the following issues:

1. Add a new Kconfig configuration for specifying Dual-redundant Core
   Lock-step (DCLS) processor topology.

2. Register initialisation is only required when Dual-redundant Core
   Lock-step (DCLS) is implemented in hardware. This initialisation is
   required on DCLS only because the architectural registers are in an
   indeterminate state after reset and therefore the initial register
   state of the two parallel executing cores are not guaranteed to be
   identical, which can lead to DCCM detecting it as a hardware fault.
   A conditional compilation check for this hardware configuration
   using the newly added CONFIG_CPU_HAS_DCLS flag has been added.

3. The existing CPU register initialisation code did not take into
   account the banked registers for every execution mode. The new
   implementation ensures that all architectural registers of every
   mode are initialised.

4. Add VFP register initialisation for when floating-point support is
   enabled and the core is configured in DCLS topology. This
   initialisation sequence is required for the same reason given in
   the first issue.

5. Add provision for platform-specific initialisation on Cortex-R
   using PLATFORM_SPECIFIC_INIT config and z_platform_init function.

6. Remove seemingly pointless and inadequately defined STACK_MARGIN.
   Not only does it violate the 8-byte stack alignment rule, it does
   not provide any form of real stack protection.

Signed-off-by: default avatarStephanos Ioannidis <root@stephanos.io>
parent 513e36e3

arch/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -414,6 +414,12 @@ config CPU_HAS_TEE 
	  Execution Environment (e.g. when it has a security attribution

	  unit).



config CPU_HAS_DCLS

	bool

	help

	  This option is enabled when the processor hardware is configured in

	  Dual-redundant Core Lock-step (DCLS) topology.



config CPU_HAS_FPU

	bool

	help

arch/arm/core/aarch32/cortex_r/reset.S

+143 −58
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2014 Wind River Systems, Inc.

 * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>

 *

 * SPDX-License-Identifier: Apache-2.0

 */
@@ -26,17 +27,17 @@ GDATA(z_arm_sys_stack) 
GDATA(z_arm_fiq_stack)

GDATA(z_arm_abort_stack)

GDATA(z_arm_undef_stack)



#define STACK_MARGIN	4



#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)

GTEXT(z_platform_init)

#endif



/**

 *

 * @brief Reset vector

 *

 * Ran when the system comes out of reset. The processor is in thread mode with

 * privileged level. At this point, the main stack pointer (MSP) is already

 * pointing to a valid area in SRAM.

 * Ran when the system comes out of reset. The processor is in Supervisor mode

 * and interrupts are disabled. The processor architectural registers are in

 * an indeterminate state.

 *

 * When these steps are completed, jump to z_arm_prep_c(), which will finish

 * setting up the system for running C code.
@@ -45,6 +46,15 @@ GDATA(z_arm_undef_stack) 
 */

SECTION_SUBSEC_FUNC(TEXT, _reset_section, z_arm_reset)

SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)



#if defined(CONFIG_CPU_HAS_DCLS)

    /*

     * Initialise CPU registers to a defined state if the processor is

     * configured as Dual-redundant Core Lock-step (DCLS). This is required

     * for state convergence of the two parallel executing cores.

     */



    /* Common and SVC mode registers */

    mov r0,  #0

    mov r1,  #0

    mov r2,  #0
@@ -58,41 +68,116 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) 
    mov r10, #0

    mov r11, #0

    mov r12, #0

	mov r14, #0

    mov r13, #0         /* r13_svc */

    mov r14, #0         /* r14_svc */

    mrs r0,  cpsr

    msr spsr_cxsf, r0   /* spsr_svc */



    /* FIQ mode registers */

    cps #MODE_FIQ

    mov r8,  #0         /* r8_fiq */

    mov r9,  #0         /* r9_fiq */

    mov r10, #0         /* r10_fiq */

    mov r11, #0         /* r11_fiq */

    mov r12, #0         /* r12_fiq */

    mov r13, #0         /* r13_fiq */

    mov r14, #0         /* r14_fiq */

    mrs r0,  cpsr

    msr spsr_cxsf, r0   /* spsr_fiq */



    /* IRQ mode registers */

    cps #MODE_IRQ

    mov r13, #0         /* r13_irq */

    mov r14, #0         /* r14_irq */

    mrs r0,  cpsr

    msr spsr_cxsf, r0   /* spsr_irq */



    /* ABT mode registers */

    cps #MODE_ABT

    mov r13, #0         /* r13_abt */

    mov r14, #0         /* r14_abt */

    mrs r0,  cpsr

    msr spsr_cxsf, r0   /* spsr_abt */



    /* UND mode registers */

    cps #MODE_UND

    mov r13, #0         /* r13_und */

    mov r14, #0         /* r14_und */

    mrs r0,  cpsr

    msr spsr_cxsf, r0   /* spsr_und */



    /* SYS mode registers */

    cps #MODE_SYS

    mov r13, #0         /* r13_sys */

    mov r14, #0         /* r14_sys */



#if defined(CONFIG_FLOAT)

    /*

     * Initialise FPU registers to a defined state.

     */



    /* Allow VFP coprocessor access */

    mrc p15, 0, r0, c1, c0, 2

    orr r0, r0, #(CPACR_CP10(CPACR_FA) | CPACR_CP11(CPACR_FA))

    mcr p15, 0, r0, c1, c0, 2



    /* Enable VFP */

    mov  r0, #FPEXC_EN

    fmxr fpexc, r0



    /* Initialise VFP registers */

    fmdrr d0,  r1, r1

    fmdrr d1,  r1, r1

    fmdrr d2,  r1, r1

    fmdrr d3,  r1, r1

    fmdrr d4,  r1, r1

    fmdrr d5,  r1, r1

    fmdrr d6,  r1, r1

    fmdrr d7,  r1, r1

    fmdrr d8,  r1, r1

    fmdrr d9,  r1, r1

    fmdrr d10, r1, r1

    fmdrr d11, r1, r1

    fmdrr d12, r1, r1

    fmdrr d13, r1, r1

    fmdrr d14, r1, r1

    fmdrr d15, r1, r1

#endif /* CONFIG_FLOAT */



#endif /* CONFIG_CPU_HAS_DCLS */



	/* lock interrupts: will get unlocked when switch to main task */

	cpsid if

    /*

     * Configure stack.

     */



	/* Setup FIQ stack */

    /* FIQ mode stack */

    msr CPSR_c, #(MODE_FIQ | I_BIT | F_BIT)

	ldr sp, =(z_arm_fiq_stack + CONFIG_ARMV7_FIQ_STACK_SIZE - STACK_MARGIN)

    ldr sp, =(z_arm_fiq_stack + CONFIG_ARMV7_FIQ_STACK_SIZE)



	/* Setup IRQ stack */

    /* IRQ mode stack */

    msr CPSR_c, #(MODE_IRQ | I_BIT | F_BIT)

	ldr sp, =(_interrupt_stack + CONFIG_ISR_STACK_SIZE - STACK_MARGIN)

    ldr sp, =(_interrupt_stack + CONFIG_ISR_STACK_SIZE)



	/* Setup data abort stack */

    /* ABT mode stack */

    msr CPSR_c, #(MODE_ABT | I_BIT | F_BIT)

	ldr sp, =(z_arm_abort_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE - \

				STACK_MARGIN)

    ldr sp, =(z_arm_abort_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE)



	/* Setup undefined mode stack */

	msr CPSR_c, #(MODE_UDF | I_BIT | F_BIT)

	ldr sp, =(z_arm_undef_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE - \

				STACK_MARGIN)

    /* UND mode stack */

    msr CPSR_c, #(MODE_UND | I_BIT | F_BIT)

    ldr sp, =(z_arm_undef_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE)



	/* Setup SVC mode stack */

    /* SVC mode stack */

    msr CPSR_c, #(MODE_SVC | I_BIT | F_BIT)

	ldr sp, =(z_arm_svc_stack + CONFIG_ARMV7_SVC_STACK_SIZE - STACK_MARGIN)

    ldr sp, =(z_arm_svc_stack + CONFIG_ARMV7_SVC_STACK_SIZE)



	/* Setup System mode stack */

    /* SYS mode stack */

    msr CPSR_c, #(MODE_SYS | I_BIT | F_BIT)

	ldr sp, =(z_arm_sys_stack + CONFIG_ARMV7_SYS_STACK_SIZE - STACK_MARGIN)

    ldr sp, =(z_arm_sys_stack + CONFIG_ARMV7_SYS_STACK_SIZE)



	/* Setup system control register */

	mrc p15, 0, r0, c1, c0, 0	/* SCTLR */

	bic r0, r0, #HIVECS		/* Exception vectors from 0-0x1c */

	mcr p15, 0, r0, c1, c0, 0

#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)

    /* Execute platform-specific initialisation if applicable */

    bl z_platform_init

#endif



#if defined(CONFIG_WDOG_INIT)

    /* board-specific watchdog initialization is necessary */

include/arch/arm/aarch32/cortex_r/cpu.h

+9 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
#define MODE_IRQ	0x12

#define MODE_SVC	0x13

#define MODE_ABT	0x17

#define MODE_UDF	0x1b

#define MODE_UND	0x1b

#define MODE_SYS	0x1f

#define MODE_MASK	0x1f
@@ -23,6 +23,14 @@ 


#define HIVECS	(1 << 13)



#define CPACR_NA	(0U)

#define CPACR_FA	(3U)



#define CPACR_CP10(r)	(r << 20)

#define CPACR_CP11(r)	(r << 22)



#define FPEXC_EN	(1 << 30)



#define RET_FROM_SVC	0

#define RET_FROM_IRQ	1

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