Commit b64c69f8 authored by Ricardo Rivera-Matos's avatar Ricardo Rivera-Matos Committed by Carles Cufi
Browse files

regulator: cp9314: Drops B0 silicon support 



Removes support for B0 revision silicon. The B0 revision is no longer
recommended for use in host-controlled applications and there are no
users of this driver implementing B0 silicon in their final design.

Signed-off-by: default avatarRicardo Rivera-Matos <rriveram@opensource.cirrus.com>
parent 2b3ed701

drivers/regulator/regulator_cp9314.c

+0 −48
Original line number Original line Diff line number Diff line
@@ -119,7 +119,6 @@ LOG_MODULE_REGISTER(CP9314, CONFIG_REGULATOR_LOG_LEVEL); 




#define CP9314_REG_BC_STS_C  0x62

#define CP9314_REG_BC_STS_C  0x62

#define CP9314_CHIP_REV_MASK GENMASK(7, 4)

#define CP9314_CHIP_REV_MASK GENMASK(7, 4)

#define CP9314_CHIP_REV_B0   0x1

#define CP9314_CHIP_REV_B1   0x3

#define CP9314_CHIP_REV_B1   0x3





#define CP9314_REG_FORCE_SC_MISC 0x69

#define CP9314_REG_FORCE_SC_MISC 0x69
@@ -222,31 +221,6 @@ struct cp9314_reg_patch { 
	uint8_t value;

	uint8_t value;

};

};





/*

 * HW errata patch for B0 silicon. Intended to correct POR configuration values for protection

 * comparators, disable OCP comparators, and enable the output undervoltage comparator.

 */

static struct cp9314_reg_patch b0_reg_patch[18] = {

	{CP9314_REG_CRUS_CTRL, GENMASK(7, 0), CP9314_CRUS_KEY_UNLOCK},

	{CP9314_REG_LION_COMP_CTRL_3, CP9314_VIN_OV_CFG, 0x1B},

	{CP9314_REG_LION_COMP_CTRL_1, CP9314_VOUT_OV_CFG_0, 0x30},

	{CP9314_REG_LION_COMP_CTRL_2, CP9314_VOUT_OV_CFG_1, 0xC},

	{CP9314_REG_VIN2OUT_OVP, CP9314_VIN2OUT_OVP, 0x2},

	{CP9314_REG_VIN2OUT_UVP, CP9314_VIN2OUT_UVP, 0x1},

	{CP9314_REG_VOUT_UVP, CP9314_VOUT_UVP_DIS, 0},

	{CP9314_REG_VOUT_UVP, CP9314_VOUT_UVP, 0},

	{CP9314_REG_LION_COMP_CTRL_1, CP9314_VIN_SWITCH_OK_DIS_0, 0},

	{CP9314_REG_LION_COMP_CTRL_4, CP9314_VIN_SWITCH_OK_DIS_1, 0},

	{CP9314_REG_LION_COMP_CTRL_1, CP9314_VIN_SWITCH_OK_CFG, 0},

	{CP9314_REG_LION_CFG_3, CP9314_LB_MIN_FREQ_SEL_0, 0x80},

	{CP9314_REG_LB_CTRL, CP9314_LB_MIN_FREQ_SEL_1, 0x4},

	{CP9314_REG_TRIM_8, CP9314_MODE_CTRL_UPDATE_BW_0, 0x2},

	{CP9314_REG_LION_CFG_3, CP9314_MODE_CTRL_UPDATE_BW_1, 0x2},

	{CP9314_REG_IIN_OCP, CP9314_IIN_OCP_DIS, CP9314_IIN_OCP_DIS},

	{CP9314_REG_IIN_PEAK_OCP, CP9314_IIN_PEAK_OCP_DIS, CP9314_IIN_PEAK_OCP_DIS},

	{CP9314_REG_CRUS_CTRL, GENMASK(7, 0), CP9314_CRUS_KEY_LOCK},

};



/* OTP memory errata patch for OTP v1. Corrects trim errata. */

/* OTP memory errata patch for OTP v1. Corrects trim errata. */

static struct cp9314_reg_patch otp_1_patch[3] = {

static struct cp9314_reg_patch otp_1_patch[3] = {

	{CP9314_REG_OPTION_REG_1, CP9314_LB1_DELAY_CFG, 0},

	{CP9314_REG_OPTION_REG_1, CP9314_LB1_DELAY_CFG, 0},
@@ -468,22 +442,6 @@ static int cp9314_cfg_sync(const struct device *dev) 
				      CP9314_FRC_SYNC_MODE);

				      CP9314_FRC_SYNC_MODE);

}

}





static int regulator_cp9314_b0_init(const struct device *dev)

{

	const struct regulator_cp9314_config *config = dev->config;

	int ret;



	for (size_t i = 0U; i < ARRAY_SIZE(b0_reg_patch); i++) {

		ret = i2c_reg_update_byte_dt(&config->i2c, b0_reg_patch[i].reg_addr,

					     b0_reg_patch[i].mask, b0_reg_patch[i].value);

		if (ret < 0) {

			return ret;

		}

	}



	return 0;

}



static int cp9314_do_soft_reset(const struct device *dev)

static int cp9314_do_soft_reset(const struct device *dev)

{

{

	const struct regulator_cp9314_config *config = dev->config;

	const struct regulator_cp9314_config *config = dev->config;
@@ -645,12 +603,6 @@ static int regulator_cp9314_init(const struct device *dev) 
	value = FIELD_GET(CP9314_CHIP_REV_MASK, value);

	value = FIELD_GET(CP9314_CHIP_REV_MASK, value);





	switch (value) {

	switch (value) {

	case CP9314_CHIP_REV_B0:

		ret = regulator_cp9314_b0_init(dev);

		if (ret < 0) {

			return ret;

		}

		break;

	case CP9314_CHIP_REV_B1:

	case CP9314_CHIP_REV_B1:

		break;

		break;

	default:

	default:

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