Commit b5c5e0e4 authored by Francois Ramu's avatar Francois Ramu Committed by Johan Hedberg
Browse files

boards: st: higher sysclock for the stm32h743/h753 nucleo boards

Configure the DTS to increase the sysclock to its max value
480MHz for the nucleo_h743zi and nucleo_h753zi boards
Max Hclock is 240MHz
The Pll source is HSE is 8MHz clock source from the STLink.

Signed-off-by: default avatarFrancois Ramu <francois.ramu@st.com>
parent 0163ae53
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+9 −9
Changes for boards/st/nucleo_h743zi/nucleo_h743zi.dts: 9 added lines, 9 removed lines.
Original line number Diff line number Diff line
@@ -80,10 +80,10 @@
};

&pll {
	div-m = <1>;
	mul-n = <24>;
	div-m = <2>;
	mul-n = <240>;
	div-p = <2>;
	div-q = <4>;
	div-q = <2>;
	div-r = <2>;
	clocks = <&clk_hse>;
	status = "okay";
@@ -91,13 +91,13 @@

&rcc {
	clocks = <&pll>;
	clock-frequency = <DT_FREQ_M(96)>;
	clock-frequency = <DT_FREQ_M(480)>;
	d1cpre = <1>;
	hpre = <1>;
	d1ppre = <1>;
	d2ppre1 = <1>;
	d2ppre2 = <1>;
	d3ppre = <1>;
	hpre = <2>;
	d1ppre = <2>;
	d2ppre1 = <2>;
	d2ppre2 = <2>;
	d3ppre = <2>;
};

&usart3 {
+9 −9
Changes for boards/st/nucleo_h753zi/nucleo_h753zi.dts: 9 added lines, 9 removed lines.
Original line number Diff line number Diff line
@@ -77,10 +77,10 @@
};

&pll {
	div-m = <1>;
	mul-n = <24>;
	div-m = <2>;
	mul-n = <240>;
	div-p = <2>;
	div-q = <4>;
	div-q = <2>;
	div-r = <2>;
	clocks = <&clk_hse>;
	status = "okay";
@@ -88,13 +88,13 @@

&rcc {
	clocks = <&pll>;
	clock-frequency = <DT_FREQ_M(96)>;
	clock-frequency = <DT_FREQ_M(480)>;
	d1cpre = <1>;
	hpre = <1>;
	d1ppre = <1>;
	d2ppre1 = <1>;
	d2ppre2 = <1>;
	d3ppre = <1>;
	hpre = <2>;
	d1ppre = <2>;
	d2ppre1 = <2>;
	d2ppre2 = <2>;
	d3ppre = <2>;
};

&usart3 {