Commit b3f0a085 authored by Alberto Escolar Piedras's avatar Alberto Escolar Piedras Committed by Alberto Escolar
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doc: nrf52_bsim: Update list of supported peripherals 



The GPIO, GPIOTE and FICR are now also modelled
to a reasonable degree.

Signed-off-by: default avatarAlberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
parent 278563ed

boards/posix/nrf52_bsim/doc/index.rst

+8 −6
Original line number Diff line number Diff line
@@ -19,16 +19,18 @@ This board models some of the NRF52 SOC peripherals: 


* Radio

* Timers

* Real time counter

* Random number generator

* RTC (Real Time Counter)

* RNG (Random Number Generator)

* AES CCM & AES ECB encryption HW

* Accelerated address resolver

* Clock control

* AAR (Accelerated Address Resolver)

* CLOCK (Clock control)

* PPI (Programmable Peripheral Interconnect)

* EGU (Event Generator Unit)

* GPIO & GPIOTE

* TEMP (Temperature sensor)

* UICR (User information configuration registers)

* NVMC (Non-volatile memory controller)

* UICR (User Information Configuration Registers)

* FICR (Factory Information Configuration Registers)

* NVMC (Non-Volatile Memory Controller)



The nrf52_bsim board definition uses the POSIX architecture to

run applications natively on the development system, this has the benefit of

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